mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-23 18:01:07 +03:00
08cf289cbd
- Replace keyword whitelist with allowlist. - Update driver to use auto-genrated regops allowlist. - This will allow support for multiple chips. Jira THWPM-14 Change-Id: I076ee1b425dfef53650477518c846e9e4d4a9e23 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2605889 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
104 lines
3.2 KiB
C
104 lines
3.2 KiB
C
/*
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* tegra-soc-hwpm-io.h:
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* This header defines register read/write APIs for the Tegra SOC HWPM driver.
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_SOC_HWPM_IO_H
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#define TEGRA_SOC_HWPM_IO_H
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#include "tegra-soc-hwpm.h"
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struct allowlist;
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struct hwpm_resource_aperture {
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/*
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* If false, this is a HWPM aperture (PERFRMON, PMA or RTR). Else this
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* is a non-HWPM aperture (ex: VIC).
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*/
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bool is_ip;
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/*
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* If is_ip == false, specify dt_aperture for readl/writel operations.
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* If is_ip == true, dt_aperture == TEGRA_SOC_HWPM_INVALID_DT.
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*/
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enum tegra_soc_hwpm_dt_aperture dt_aperture;
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/* Physical aperture */
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u64 start_abs_pa;
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u64 end_abs_pa;
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u64 start_pa;
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u64 end_pa;
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/* Allowlist */
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struct allowlist *alist;
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u64 alist_size;
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/* Fake registers for VDK which doesn't have a SOC HWPM fmodel */
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u32 *fake_registers;
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};
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struct hwpm_resource {
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bool reserved;
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u32 map_size;
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struct hwpm_resource_aperture *map;
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};
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/* Externs */
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extern struct hwpm_resource hwpm_resources[TERGA_SOC_HWPM_NUM_RESOURCES];
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extern u32 *pma_fake_regs;
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extern u32 *mc_fake_regs[16];
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extern struct hwpm_resource_aperture mss_channel_map[];
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extern struct hwpm_resource_aperture mss_iso_niso_hub_map[];
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extern struct hwpm_resource_aperture mss_mcf_map[];
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extern struct hwpm_resource_aperture pma_map[];
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extern struct hwpm_resource_aperture cmd_slice_rtr_map[];
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void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture);
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int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm,
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u64 phys_addr,
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bool use_absolute_base,
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bool check_reservation,
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u64 *updated_pa);
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u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u32 reg_offset);
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void hwpm_writel(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u32 reg_offset, u32 val);
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u32 ip_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr);
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void ip_writel(struct tegra_soc_hwpm *hwpm, u64 phys_addr, u32 val);
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u32 ioctl_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr);
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void ioctl_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr,
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u32 val);
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int reg_rmw(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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enum tegra_soc_hwpm_dt_aperture dt_aperture,
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u64 addr,
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u32 field_mask,
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u32 field_val,
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bool is_ioctl,
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bool is_ip);
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#endif /* TEGRA_SOC_HWPM_IO_H */
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