mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-24 02:07:34 +03:00
579bc23ee6
Add support for IP registering mechanism for runtime callback and perfmux read/writes. void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops); IP's callback are called to disable and enable IP runtime pm. At this moment, only VIC/NVENC/OFA driver registration is supported. Also will take-up perfmux register read/write in follow-up patch. Bug 3333031 Bug 3333042 Change-Id: If559cae73be1edbdb7139b4183ce3e1dc0943053 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2607267 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* tegra-soc-hwpm-ip.c:
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* This file contains functions for SOC HWPM <-> IPC communication.
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*/
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include "tegra-soc-hwpm.h"
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struct platform_device *tegra_soc_hwpm_pdev;
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static enum tegra_soc_hwpm_dt_aperture tegra_soc_hwpm_get_apeture(
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struct tegra_soc_hwpm *hwpm, u64 ip_base_address)
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{
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enum tegra_soc_hwpm_dt_aperture aperture =
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TEGRA_SOC_HWPM_NUM_DT_APERTURES;
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/* TODO chip speciifc implementation for finding aperture */
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if (ip_base_address == addr_map_vic_base_r()) {
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aperture = TEGRA_SOC_HWPM_VICA0_PERFMON_DT;
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} else if (ip_base_address == addr_map_nvenc_base_r()) {
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aperture = TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT;
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} else if (ip_base_address == addr_map_ofa_base_r()) {
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aperture = TEGRA_SOC_HWPM_OFAA0_PERFMON_DT;
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}
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return aperture;
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}
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void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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enum tegra_soc_hwpm_dt_aperture dt_aperture;
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tegra_soc_hwpm_dbg("HWPM Registered IP 0x%llx",
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hwpm_ip_ops->ip_base_address);
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_soc_hwpm_err(
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"IP trying to register before SOC HWPM 0x%llx",
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hwpm_ip_ops->ip_base_address);
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} else {
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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dt_aperture = tegra_soc_hwpm_get_apeture(hwpm,
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hwpm_ip_ops->ip_base_address);
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if (dt_aperture != TEGRA_SOC_HWPM_NUM_DT_APERTURES) {
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memcpy(&hwpm->ip_info[dt_aperture], hwpm_ip_ops,
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sizeof(struct tegra_soc_hwpm_ip_ops));
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} else {
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tegra_soc_hwpm_err(
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"SOC HWPM has no support for 0x%llx",
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hwpm_ip_ops->ip_base_address);
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}
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}
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}
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void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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enum tegra_soc_hwpm_dt_aperture dt_aperture;
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_soc_hwpm_err("IP unregister before SOC HWPM 0x%llx",
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hwpm_ip_ops->ip_base_address);
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} else {
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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dt_aperture = tegra_soc_hwpm_get_apeture(hwpm,
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hwpm_ip_ops->ip_base_address);
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if (dt_aperture != TEGRA_SOC_HWPM_NUM_DT_APERTURES) {
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memset(&hwpm->ip_info[dt_aperture], 0,
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sizeof(struct tegra_soc_hwpm_ip_ops));
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}
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}
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}
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