mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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0cb6f6b48f
- Generate HWPM hw headers using register generator tool. - Add required hw headers to include/hw/ path - Update driver code to replace static hw defines with hw header definitions. - Remove unused static hw defines. THWPM-39 Change-Id: I57566d51657bb6b22c4b581acd257f1871438adf Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2552741 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
177 lines
11 KiB
C
177 lines
11 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Function/Macro naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef TEGRA_HW_PMASYS_SOC_HWPM_H
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#define TEGRA_HW_PMASYS_SOC_HWPM_H
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#define pmasys_cg2_r() (0x0f14a044U)
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#define pmasys_cg2_slcg_f(v) (((v) & 0x1U) << 0U)
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#define pmasys_cg2_slcg_m() (0x1U << 0U)
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#define pmasys_cg2_slcg_enabled_v() (0x00000000U)
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#define pmasys_cg2_slcg_enabled_f() (0x0U)
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#define pmasys_cg2_slcg_disabled_v() (0x00000001U)
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#define pmasys_cg2_slcg_disabled_f() (0x1U)
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#define pmasys_controlb_r() (0x0f14a070U)
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#define pmasys_controlb_coalesce_timeout_cycles_f(v) (((v) & 0x7U) << 4U)
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#define pmasys_controlb_coalesce_timeout_cycles_m() (0x7U << 4U)
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#define pmasys_controlb_coalesce_timeout_cycles__prod_f() (0x40U)
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#define pmasys_channel_status_secure_r(i)\
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(0x0f14a610U + ((i)*384U))
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#define pmasys_channel_status_secure_membuf_status_f(v) (((v) & 0x1U) << 0U)
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#define pmasys_channel_status_secure_membuf_status_m() (0x1U << 0U)
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#define pmasys_channel_status_secure_membuf_status_v(r) (((r) >> 0U) & 0x1U)
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#define pmasys_channel_status_secure_membuf_status_init_v() (0x00000000U)
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#define pmasys_channel_status_secure_membuf_status_overflowed_v() (0x00000001U)
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#define pmasys_channel_control_user_r(i)\
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(0x0f14a620U + ((i)*384U))
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#define pmasys_channel_control_user_stream_f(v) (((v) & 0x1U) << 0U)
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#define pmasys_channel_control_user_stream_m() (0x1U << 0U)
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#define pmasys_channel_control_user_stream_disable_v() (0x00000000U)
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#define pmasys_channel_control_user_stream_disable_f() (0x0U)
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#define pmasys_channel_control_user_stream_enable_v() (0x00000001U)
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#define pmasys_channel_control_user_update_bytes_f(v) (((v) & 0x1U) << 31U)
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#define pmasys_channel_control_user_update_bytes_m() (0x1U << 31U)
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#define pmasys_channel_control_user_update_bytes_doit_v() (0x00000001U)
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#define pmasys_channel_control_user_update_bytes_doit_f() (0x80000000U)
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#define pmasys_channel_mem_bump_r(i)\
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(0x0f14a624U + ((i)*4U))
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#define pmasys_channel_mem_block_r(i)\
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(0x0f14a638U + ((i)*4U))
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#define pmasys_channel_mem_block__size_1_v() (0x00000001U)
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#define pmasys_channel_mem_block_ptr_f(v) (((v) & 0x3fffffffU) << 0U)
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#define pmasys_channel_mem_block_ptr_m() (0x3fffffffU << 0U)
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#define pmasys_channel_mem_block_base_f(v) (((v) & 0xfffffffU) << 0U)
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#define pmasys_channel_mem_block_base_m() (0xfffffffU << 0U)
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#define pmasys_channel_mem_block_target_f(v) (((v) & 0x3U) << 28U)
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#define pmasys_channel_mem_block_target_m() (0x3U << 28U)
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#define pmasys_channel_mem_block_target_lfb_v() (0x00000000U)
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#define pmasys_channel_mem_block_target_sys_coh_v() (0x00000002U)
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#define pmasys_channel_mem_block_target_sys_ncoh_v() (0x00000003U)
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#define pmasys_channel_mem_block_valid_f(v) (((v) & 0x1U) << 31U)
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#define pmasys_channel_mem_block_valid_m() (0x1U << 31U)
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#define pmasys_channel_mem_block_valid_false_v() (0x00000000U)
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#define pmasys_channel_mem_block_valid_true_v() (0x00000001U)
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#define pmasys_channel_config_user_r(i)\
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(0x0f14a640U + ((i)*384U))
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#define pmasys_channel_config_user_coalesce_timeout_cycles_f(v)\
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(((v) & 0x7U) << 4U)
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#define pmasys_channel_config_user_coalesce_timeout_cycles_m() (0x7U << 4U)
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#define pmasys_channel_config_user_coalesce_timeout_cycles__prod_v()\
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(0x00000004U)
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#define pmasys_channel_config_user_coalesce_timeout_cycles__prod_f() (0x40U)
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#define pmasys_channel_outbase_r(i)\
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(0x0f14a644U + ((i)*4U))
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#define pmasys_channel_outbase_ptr_f(v) (((v) & 0x7ffffffU) << 5U)
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#define pmasys_channel_outbase_ptr_m() (0x7ffffffU << 5U)
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#define pmasys_channel_outbase_ptr_v(r) (((r) >> 5U) & 0x7ffffffU)
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#define pmasys_channel_outbaseupper_r(i)\
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(0x0f14a648U + ((i)*4U))
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#define pmasys_channel_outbaseupper_ptr_f(v) (((v) & 0xffU) << 0U)
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#define pmasys_channel_outbaseupper_ptr_m() (0xffU << 0U)
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#define pmasys_channel_outbaseupper_ptr_v(r) (((r) >> 0U) & 0xffU)
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#define pmasys_channel_outsize_r(i)\
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(0x0f14a64cU + ((i)*4U))
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#define pmasys_channel_outsize_numbytes_f(v) (((v) & 0x7ffffffU) << 5U)
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#define pmasys_channel_outsize_numbytes_m() (0x7ffffffU << 5U)
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#define pmasys_channel_mem_head_r(i)\
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(0x0f14a650U + ((i)*4U))
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#define pmasys_channel_mem_bytes_addr_r(i)\
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(0x0f14a658U + ((i)*4U))
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#define pmasys_channel_mem_bytes_addr_ptr_f(v) (((v) & 0x3fffffffU) << 2U)
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#define pmasys_channel_mem_bytes_addr_ptr_m() (0x3fffffffU << 2U)
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#define pmasys_trigger_config_user_r(i)\
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(0x0f14a694U + ((i)*384U))
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#define pmasys_trigger_config_user_pma_pulse_f(v) (((v) & 0x1U) << 0U)
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#define pmasys_trigger_config_user_pma_pulse_m() (0x1U << 0U)
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#define pmasys_trigger_config_user_pma_pulse_disable_v() (0x00000000U)
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#define pmasys_trigger_config_user_pma_pulse_disable_f() (0x0U)
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#define pmasys_trigger_config_user_pma_pulse_enable_v() (0x00000001U)
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#define pmasys_trigger_config_user_record_stream_f(v) (((v) & 0x1U) << 6U)
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#define pmasys_trigger_config_user_record_stream_m() (0x1U << 6U)
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#define pmasys_trigger_config_user_record_stream_disable_v() (0x00000000U)
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#define pmasys_trigger_config_user_record_stream_disable_f() (0x0U)
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#define pmasys_trigger_config_user_record_stream_enable_v() (0x00000001U)
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#define pmasys_enginestatus_r() (0x0f14a75cU)
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#define pmasys_enginestatus_status_s() (3U)
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#define pmasys_enginestatus_status_f(v) (((v) & 0x7U) << 0U)
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#define pmasys_enginestatus_status_m() (0x7U << 0U)
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#define pmasys_enginestatus_status_v(r) (((r) >> 0U) & 0x7U)
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#define pmasys_enginestatus_status_w() (0U)
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#define pmasys_enginestatus_status_empty_v() (0x00000000U)
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#define pmasys_enginestatus_status_empty_f() (0x0U)
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#define pmasys_enginestatus_status_active_v() (0x00000001U)
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#define pmasys_enginestatus_status_paused_v() (0x00000002U)
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#define pmasys_enginestatus_status_quiescent_v() (0x00000003U)
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#define pmasys_enginestatus_status_stalled_v() (0x00000005U)
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#define pmasys_enginestatus_status_faulted_v() (0x00000006U)
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#define pmasys_enginestatus_status_halted_v() (0x00000007U)
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#define pmasys_enginestatus_rbufempty_s() (1U)
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#define pmasys_enginestatus_rbufempty_f(v) (((v) & 0x1U) << 4U)
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#define pmasys_enginestatus_rbufempty_m() (0x1U << 4U)
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#define pmasys_enginestatus_rbufempty_v(r) (((r) >> 4U) & 0x1U)
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#define pmasys_enginestatus_rbufempty_w() (0U)
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#define pmasys_enginestatus_rbufempty_empty_v() (0x00000001U)
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#define pmasys_enginestatus_rbufempty_empty_f() (0x10U)
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#define pmasys_enginestatus_mbu_status_f(v) (((v) & 0x3U) << 5U)
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#define pmasys_enginestatus_mbu_status_m() (0x3U << 5U)
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#define pmasys_enginestatus_mbu_status_idle_v() (0x00000000U)
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#define pmasys_enginestatus_mbu_status_busy_v() (0x00000001U)
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#define pmasys_enginestatus_mbu_status_pending_v() (0x00000002U)
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#define pmasys_sys_trigger_start_mask_r() (0x0f14a66cU)
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#define pmasys_sys_trigger_start_maskb_r() (0x0f14a670U)
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#define pmasys_sys_trigger_stop_mask_r() (0x0f14a684U)
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#define pmasys_sys_trigger_stop_maskb_r() (0x0f14a688U)
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#endif
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