mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 09:12:05 +03:00
106bc61f86
Add new CPU IP and resource enum in kernel driver and userspace library. This is to extend support for chips with more than 32 CPU instances (up to 128). JIRA MSST-893 Change-Id: I33142c7fc8f268f8c436cc3b7cd97385da31b558 Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3328654 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Yifei Wan <ywan@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com>
576 lines
15 KiB
C
576 lines
15 KiB
C
/* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: GPL-2.0-only
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/slab.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_kmem.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <os/linux/ip_utils.h>
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#include <os/linux/driver.h>
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struct platform_device *tegra_soc_hwpm_pdev;
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struct hwpm_ip_register_list *ip_register_list_head;
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#define REGISTER_IP true
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#define UNREGISTER_IP false
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static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_ip ip_enum)
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{
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u32 ip_enum_idx = TEGRA_HWPM_IP_INACTIVE;
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switch (ip_enum) {
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case TEGRA_SOC_HWPM_IP_VI:
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ip_enum_idx = TEGRA_HWPM_IP_VI;
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break;
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case TEGRA_SOC_HWPM_IP_ISP:
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ip_enum_idx = TEGRA_HWPM_IP_ISP;
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break;
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case TEGRA_SOC_HWPM_IP_VIC:
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ip_enum_idx = TEGRA_HWPM_IP_VIC;
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break;
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case TEGRA_SOC_HWPM_IP_OFA:
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ip_enum_idx = TEGRA_HWPM_IP_OFA;
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break;
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case TEGRA_SOC_HWPM_IP_PVA:
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ip_enum_idx = TEGRA_HWPM_IP_PVA;
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break;
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case TEGRA_SOC_HWPM_IP_NVDLA:
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ip_enum_idx = TEGRA_HWPM_IP_NVDLA;
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break;
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case TEGRA_SOC_HWPM_IP_MGBE:
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ip_enum_idx = TEGRA_HWPM_IP_MGBE;
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break;
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case TEGRA_SOC_HWPM_IP_SCF:
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ip_enum_idx = TEGRA_HWPM_IP_SCF;
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break;
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case TEGRA_SOC_HWPM_IP_NVDEC:
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ip_enum_idx = TEGRA_HWPM_IP_NVDEC;
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break;
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case TEGRA_SOC_HWPM_IP_NVENC:
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ip_enum_idx = TEGRA_HWPM_IP_NVENC;
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break;
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case TEGRA_SOC_HWPM_IP_PCIE:
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ip_enum_idx = TEGRA_HWPM_IP_PCIE;
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break;
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case TEGRA_SOC_HWPM_IP_DISPLAY:
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ip_enum_idx = TEGRA_HWPM_IP_DISPLAY;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_CHANNEL:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_CHANNEL;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_GPU_HUB:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_GPU_HUB;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_MCF:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_MCF;
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break;
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case TEGRA_SOC_HWPM_IP_APE:
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ip_enum_idx = TEGRA_HWPM_IP_APE;
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break;
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case TEGRA_SOC_HWPM_IP_C2C:
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ip_enum_idx = TEGRA_HWPM_IP_C2C;
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break;
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case TEGRA_SOC_HWPM_IP_SMMU:
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ip_enum_idx = TEGRA_HWPM_IP_SMMU;
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break;
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case TEGRA_SOC_HWPM_IP_CL2:
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ip_enum_idx = TEGRA_HWPM_IP_CL2;
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break;
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case TEGRA_SOC_HWPM_IP_NVLCTRL:
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ip_enum_idx = TEGRA_HWPM_IP_NVLCTRL;
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break;
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case TEGRA_SOC_HWPM_IP_NVLRX:
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ip_enum_idx = TEGRA_HWPM_IP_NVLRX;
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break;
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case TEGRA_SOC_HWPM_IP_NVLTX:
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ip_enum_idx = TEGRA_HWPM_IP_NVLTX;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_HUB:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_HUB;
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break;
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case TEGRA_SOC_HWPM_IP_MCF_SOC:
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ip_enum_idx = TEGRA_HWPM_IP_MCF_SOC;
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break;
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case TEGRA_SOC_HWPM_IP_MCF_C2C:
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ip_enum_idx = TEGRA_HWPM_IP_MCF_C2C;
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break;
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case TEGRA_SOC_HWPM_IP_MCF_CLINK:
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ip_enum_idx = TEGRA_HWPM_IP_MCF_CLINK;
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break;
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case TEGRA_SOC_HWPM_IP_MCF_CORE:
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ip_enum_idx = TEGRA_HWPM_IP_MCF_CORE;
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break;
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case TEGRA_SOC_HWPM_IP_MCF_OCU:
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ip_enum_idx = TEGRA_HWPM_IP_MCF_OCU;
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break;
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case TEGRA_SOC_HWPM_IP_PCIE_XTLQ:
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ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLQ;
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break;
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case TEGRA_SOC_HWPM_IP_PCIE_XTLRC:
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ip_enum_idx = TEGRA_HWPM_IP_PCIE_XTLRC;
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break;
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case TEGRA_SOC_HWPM_IP_PCIE_XALRC:
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ip_enum_idx = TEGRA_HWPM_IP_PCIE_XALRC;
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break;
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case TEGRA_SOC_HWPM_IP_UCF_MSW:
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ip_enum_idx = TEGRA_HWPM_IP_UCF_MSW;
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break;
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case TEGRA_SOC_HWPM_IP_UCF_PSW:
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ip_enum_idx = TEGRA_HWPM_IP_UCF_PSW;
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break;
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case TEGRA_SOC_HWPM_IP_UCF_CSW:
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ip_enum_idx = TEGRA_HWPM_IP_UCF_CSW;
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break;
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case TEGRA_SOC_HWPM_IP_UCF_HUB:
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ip_enum_idx = TEGRA_HWPM_IP_UCF_HUB;
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break;
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case TEGRA_SOC_HWPM_IP_UCF_SCB:
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ip_enum_idx = TEGRA_HWPM_IP_UCF_SCB;
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break;
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case TEGRA_SOC_HWPM_IP_CPU:
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ip_enum_idx = TEGRA_HWPM_IP_CPU;
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break;
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case TEGRA_SOC_HWPM_IP_CPU_EXT_0:
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ip_enum_idx = TEGRA_HWPM_IP_CPU_EXT_0;
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break;
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case TEGRA_SOC_HWPM_IP_CPU_EXT_1:
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ip_enum_idx = TEGRA_HWPM_IP_CPU_EXT_1;
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break;
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case TEGRA_SOC_HWPM_IP_CPU_EXT_2:
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ip_enum_idx = TEGRA_HWPM_IP_CPU_EXT_2;
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break;
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case TEGRA_SOC_HWPM_IP_NVTHERM:
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ip_enum_idx = TEGRA_HWPM_IP_NVTHERM;
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break;
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case TEGRA_SOC_HWPM_IP_CSN:
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ip_enum_idx = TEGRA_HWPM_IP_CSN;
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break;
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case TEGRA_SOC_HWPM_IP_CSN_EXT_0:
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ip_enum_idx = TEGRA_HWPM_IP_CSN_EXT_0;
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break;
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case TEGRA_SOC_HWPM_IP_CSNH:
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ip_enum_idx = TEGRA_HWPM_IP_CSNH;
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break;
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default:
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tegra_hwpm_err(hwpm,
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"Queried enum tegra_soc_hwpm_ip %d is invalid",
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ip_enum);
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break;
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}
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return ip_enum_idx;
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}
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int tegra_hwpm_obtain_floorsweep_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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for (i = 0U; i < fs_info->num_queries; i++) {
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ret = hwpm->active_chip->get_fs_info(hwpm,
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tegra_hwpm_translate_soc_hwpm_ip(
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hwpm, fs_info->ip_fsinfo[i].ip),
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&fs_info->ip_fsinfo[i].ip_inst_mask,
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&fs_info->ip_fsinfo[i].status);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Failed to get fs_info query %d", i);
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}
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_floorsweep_info,
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"Query %d: tegra_soc_hwpm_ip %d: ip_status: %d"
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" inst_mask 0x%llx",
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i, fs_info->ip_fsinfo[i].ip,
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fs_info->ip_fsinfo[i].status,
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fs_info->ip_fsinfo[i].ip_inst_mask);
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}
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return ret;
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}
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u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_resource res_enum)
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{
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u32 res_enum_idx = TEGRA_HWPM_IP_INACTIVE;
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switch (res_enum) {
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case TEGRA_SOC_HWPM_RESOURCE_VI:
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res_enum_idx = TEGRA_HWPM_RESOURCE_VI;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_ISP:
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res_enum_idx = TEGRA_HWPM_RESOURCE_ISP;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_VIC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_VIC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_OFA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_OFA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PVA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PVA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVDLA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVDLA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MGBE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MGBE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_SCF:
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res_enum_idx = TEGRA_HWPM_RESOURCE_SCF;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVDEC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVDEC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVENC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVENC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PCIE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_DISPLAY:
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res_enum_idx = TEGRA_HWPM_RESOURCE_DISPLAY;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_CHANNEL;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_GPU_HUB;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_ISO_NISO_HUBS;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_MCF:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_MCF;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PMA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PMA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_APE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_APE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_C2C:
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res_enum_idx = TEGRA_HWPM_RESOURCE_C2C;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_SMMU:
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res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CL2:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CL2;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLCTRL:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLCTRL;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLRX:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLRX;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLTX:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLTX;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_HUB:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_HUB;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MCF_SOC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_SOC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MCF_C2C:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_C2C;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MCF_CLINK:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_CLINK;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MCF_CORE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_CORE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MCF_OCU:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MCF_OCU;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLQ:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLQ;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PCIE_XTLRC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XTLRC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PCIE_XALRC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE_XALRC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_UCF_MSW:
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res_enum_idx = TEGRA_HWPM_RESOURCE_UCF_MSW;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_UCF_PSW:
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res_enum_idx = TEGRA_HWPM_RESOURCE_UCF_PSW;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_UCF_CSW:
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res_enum_idx = TEGRA_HWPM_RESOURCE_UCF_CSW;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_UCF_HUB:
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res_enum_idx = TEGRA_HWPM_RESOURCE_UCF_HUB;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_UCF_SCB:
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res_enum_idx = TEGRA_HWPM_RESOURCE_UCF_SCB;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CPU:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CPU;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CPU_EXT_0:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CPU_EXT_0;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CPU_EXT_1:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CPU_EXT_1;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CPU_EXT_2:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CPU_EXT_2;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVTHERM:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVTHERM;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CSN:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CSN;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CSN_EXT_0:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CSN_EXT_0;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CSNH:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CSNH;
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break;
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default:
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tegra_hwpm_err(hwpm,
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"Queried enum tegra_soc_hwpm_resource %d is invalid",
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res_enum);
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break;
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}
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return res_enum_idx;
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}
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int tegra_hwpm_obtain_resource_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_resource_info *rsrc_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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for (i = 0U; i < rsrc_info->num_queries; i++) {
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ret = hwpm->active_chip->get_resource_info(
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hwpm, tegra_hwpm_translate_soc_hwpm_resource(
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hwpm, rsrc_info->resource_info[i].resource),
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&rsrc_info->resource_info[i].status);
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if (ret < 0) {
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/* Print error for debug purpose. */
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tegra_hwpm_err(hwpm, "Failed to get rsrc_info");
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}
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_resource_info,
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"Query %d: resource %d: status: %d",
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i, rsrc_info->resource_info[i].resource,
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rsrc_info->resource_info[i].status);
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}
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return ret;
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}
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static int tegra_hwpm_record_ip_ops(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_ops *soc_ip_ops, bool available)
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{
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struct tegra_hwpm_ip_ops ip_ops;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
ip_ops.ip_dev = soc_ip_ops->ip_dev;
|
|
ip_ops.hwpm_ip_pm = soc_ip_ops->hwpm_ip_pm;
|
|
ip_ops.hwpm_ip_reg_op = soc_ip_ops->hwpm_ip_reg_op;
|
|
|
|
if (soc_ip_ops->resource_enum >= TERGA_SOC_HWPM_NUM_RESOURCES) {
|
|
tegra_hwpm_err(hwpm, "resource enum %d out of scope",
|
|
soc_ip_ops->resource_enum);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return hwpm->active_chip->extract_ip_ops(hwpm,
|
|
tegra_hwpm_translate_soc_hwpm_resource(hwpm,
|
|
(enum tegra_soc_hwpm_resource)soc_ip_ops->resource_enum),
|
|
soc_ip_ops->ip_base_address,
|
|
&ip_ops, available);
|
|
}
|
|
|
|
int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm)
|
|
{
|
|
int ret = 0;
|
|
struct hwpm_ip_register_list *node = ip_register_list_head;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
while (node != NULL) {
|
|
ret = tegra_hwpm_record_ip_ops(hwpm, &node->ip_ops, REGISTER_IP);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"Resource enum %d extract IP ops failed",
|
|
node->ip_ops.resource_enum);
|
|
return ret;
|
|
}
|
|
node = node->next;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_hwpm_alloc_ip_register_list_node(
|
|
struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops,
|
|
struct hwpm_ip_register_list **node_ptr)
|
|
{
|
|
struct hwpm_ip_register_list *new_node = NULL;
|
|
|
|
new_node = tegra_hwpm_kzalloc(NULL,
|
|
sizeof(struct hwpm_ip_register_list));
|
|
if (new_node == NULL) {
|
|
tegra_hwpm_err(NULL,
|
|
"struct hwpm_ip_register_list node allocation failed");
|
|
return -ENOMEM;
|
|
}
|
|
new_node->next = NULL;
|
|
|
|
/* Copy given ip register details to node */
|
|
memcpy(&new_node->ip_ops, hwpm_ip_ops,
|
|
sizeof(struct tegra_soc_hwpm_ip_ops));
|
|
(*node_ptr) = new_node;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_hwpm_note_ip_register(
|
|
struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
|
|
{
|
|
int err = 0;
|
|
struct hwpm_ip_register_list *node;
|
|
|
|
if (ip_register_list_head == NULL) {
|
|
err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
|
|
&ip_register_list_head);
|
|
if (err != 0) {
|
|
tegra_hwpm_err(NULL,
|
|
"failed to note ip registration");
|
|
return err;
|
|
}
|
|
} else {
|
|
node = ip_register_list_head;
|
|
while (node->next != NULL) {
|
|
node = node->next;
|
|
}
|
|
|
|
err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
|
|
&node->next);
|
|
if (err != 0) {
|
|
tegra_hwpm_err(NULL,
|
|
"failed to note ip registration");
|
|
return err;
|
|
}
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
|
|
{
|
|
struct tegra_soc_hwpm *hwpm = NULL;
|
|
int ret = 0;
|
|
|
|
if (hwpm_ip_ops == NULL) {
|
|
tegra_hwpm_err(NULL, "IP details missing");
|
|
return;
|
|
}
|
|
|
|
if (tegra_soc_hwpm_pdev == NULL) {
|
|
tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
|
|
"Noting IP 0x%llx register request",
|
|
hwpm_ip_ops->ip_base_address);
|
|
ret = tegra_hwpm_note_ip_register(hwpm_ip_ops);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(NULL,
|
|
"Couldn't save IP register details");
|
|
return;
|
|
}
|
|
} else {
|
|
if (hwpm_ip_ops->ip_dev == NULL) {
|
|
tegra_hwpm_err(hwpm, "IP dev to register is NULL");
|
|
return;
|
|
}
|
|
hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
|
|
"Register IP 0x%llx", hwpm_ip_ops->ip_base_address);
|
|
|
|
ret = tegra_hwpm_record_ip_ops(hwpm, hwpm_ip_ops, REGISTER_IP);
|
|
if (ret < 0) {
|
|
tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
|
|
hwpm_ip_ops->resource_enum);
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(tegra_soc_hwpm_ip_register);
|
|
|
|
void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
|
|
{
|
|
struct tegra_soc_hwpm *hwpm = NULL;
|
|
int ret = 0;
|
|
|
|
if (hwpm_ip_ops == NULL) {
|
|
tegra_hwpm_err(NULL, "IP details missing");
|
|
return;
|
|
}
|
|
|
|
if (tegra_soc_hwpm_pdev == NULL) {
|
|
tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
|
|
"HWPM device not available");
|
|
} else {
|
|
if (hwpm_ip_ops->ip_dev == NULL) {
|
|
tegra_hwpm_err(hwpm, "IP dev to unregister is NULL");
|
|
return;
|
|
}
|
|
hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
|
|
"Unregister IP 0x%llx", hwpm_ip_ops->ip_base_address);
|
|
|
|
ret = tegra_hwpm_record_ip_ops(hwpm, hwpm_ip_ops, UNREGISTER_IP);
|
|
if (ret < 0) {
|
|
tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
|
|
hwpm_ip_ops->resource_enum);
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL(tegra_soc_hwpm_ip_unregister);
|
|
|
|
void tegra_hwpm_release_ip_register_node(struct tegra_soc_hwpm *hwpm)
|
|
{
|
|
struct hwpm_ip_register_list *node = ip_register_list_head;
|
|
struct hwpm_ip_register_list *tmp_node = NULL;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
while (node != NULL) {
|
|
tmp_node = node;
|
|
node = tmp_node->next;
|
|
tegra_hwpm_kfree(hwpm, tmp_node);
|
|
}
|
|
}
|