mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-24 02:07:34 +03:00
378bd9bb1c
To make HWPM driver OS agnostic, remove linux specific includes from common and chip specific files. - Move IP register list related logic to os linux folder. - tegra_hwpm_get_floorsweep_info() and tegra_hwpm_get_resource_info() refer to linux specific UAPI structures. Relocate these functions to os folder. - Use tegra_hwpm_ip_ops structure in HWPM driver internal logic. Move or rewrite functions using tegra_soc_hwpm_ip_ops. Jira THWPM-59 Change-Id: I1dd1e088d59fdc44923d2b6502bb0cf350ce57a6 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2729471 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_internal.h>
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#include <hal/t234/hw/t234_pmasys_soc_hwpm.h>
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#include <hal/t234/hw/t234_pmmsys_soc_hwpm.h>
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int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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/* Enable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_bind,
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"Enabling PERFMON(0x%llx - 0x%llx)",
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perfmon->start_abs_pa, perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_sys0_enginestatus_enable_m(),
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pmmsys_sys0_enginestatus_enable_out_f());
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err = tegra_hwpm_writel(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_perfmux_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmux)
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{
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tegra_hwpm_fn(hwpm, " ");
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return 0;
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}
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int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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if (perfmon->element_type == HWPM_ELEMENT_PERFMUX) {
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/*
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* Since HWPM elements use perfmon functions,
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* skip disabling HWPM PERFMUX elements
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*/
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return 0;
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}
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/* Disable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_release_resource,
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"Disabling PERFMON(0x%llx - 0x%llx)",
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perfmon->start_abs_pa, perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_control_mode_m(),
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pmmsys_control_mode_disable_f());
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err = tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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