mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-24 10:13:00 +03:00
10cd01aa1a
- Some of the APIs are not available on stable kernel. Use kstable specific APIs with LINUX_KERNEL macro condition. - Temporarily comment functions that are not available on Kstable. - Next chip headers are renamed to accommodate more than one next chip. Update next chip includes in init.c and driver.c files. - Rename TEGRA_SOC_HWPM_IP_INACTIVE to TEGRA_HWPM_IP_INACTIVE to follow other macro/enum naming convention. - Use is_resource_active() HAL instead of chip specific function. - Create clock reset functions that will allow us to handle change in APIs on kstable. Jira THWPM-41 Change-Id: I55f58fa51cf9ae96ee9a9565942e68b3b2bb76ee Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2764840 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
114 lines
2.4 KiB
C
114 lines
2.4 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef TEGRA_HWPM_SOC_H
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#define TEGRA_HWPM_SOC_H
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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#define PLAT_SI 0
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#define PLAT_PRE_SI_QT 1
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#define PLAT_PRE_SI_VDK 8
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#define PLAT_PRE_SI_VSP 9
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#define PLAT_INVALID 10
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#define TEGRA_FUSE_PRODUCTION_MODE 0x0
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#endif
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#ifdef __KERNEL__
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#include <os/linux/soc_utils.h>
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#else
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u32 tegra_hwpm_get_chip_id_impl(void)
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{
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return 0U;
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}
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u32 tegra_hwpm_get_major_rev_impl(void)
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{
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return 0U;
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}
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u32 tegra_hwpm_chip_get_revision_impl(void)
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{
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return 0U;
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}
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u32 tegra_hwpm_get_platform_impl(void)
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{
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return 0U;
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}
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bool tegra_hwpm_is_platform_simulation_impl(void)
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{
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return false;
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}
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bool tegra_hwpm_is_platform_vsp_impl(void)
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{
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return false;
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}
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bool tegra_hwpm_is_platform_silicon_impl(void)
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{
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return true;
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}
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bool tegra_hwpm_is_hypervisor_mode_impl(void)
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{
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return false;
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}
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int tegra_hwpm_fuse_readl_impl(struct tegra_soc_hwpm *hwpm,
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u64 reg_offset, u32 *val)
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{
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return -EINVAL;
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}
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int tegra_hwpm_fuse_readl_prod_mode_impl(struct tegra_soc_hwpm *hwpm, u32 *val)
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{
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return -EINVAL;
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}
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#endif
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#define tegra_hwpm_get_chip_id() \
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tegra_hwpm_get_chip_id_impl()
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#define tegra_hwpm_get_major_rev() \
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tegra_hwpm_get_major_rev_impl()
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#define tegra_hwpm_chip_get_revision() \
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tegra_hwpm_chip_get_revision_impl()
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#define tegra_hwpm_get_platform() \
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tegra_hwpm_get_platform_impl()
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#define tegra_hwpm_is_platform_simulation() \
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tegra_hwpm_is_platform_simulation_impl()
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#define tegra_hwpm_is_platform_vsp() \
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tegra_hwpm_is_platform_vsp_impl()
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#define tegra_hwpm_is_platform_silicon() \
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tegra_hwpm_is_platform_silicon_impl()
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#define tegra_hwpm_is_hypervisor_mode() \
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tegra_hwpm_is_hypervisor_mode_impl()
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#define tegra_hwpm_fuse_readl(hwpm, reg_offset, val) \
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tegra_hwpm_fuse_readl_impl(hwpm, reg_offset, val)
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#define tegra_hwpm_fuse_readl_prod_mode(hwpm, val) \
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tegra_hwpm_fuse_readl_prod_mode_impl(hwpm, val)
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#endif /* TEGRA_HWPM_SOC_H */
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