mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 09:12:05 +03:00
14d527e97a
- Declare and initialize timeout and mem_bytes_kernel_u32 variables. - alist_map NULL pointer check is done after alist_map structure references. Modify update_allowlist ioctl and release alist_map functions to check alist_map NULL pointer before it's use. - Checking if unsigned _IOC_NR(cmd) is less than zero has no effect. Remove this check. - Correct printf format specifier for mem_bytes_addr. Bug 3461002 Change-Id: I79a97942e667c173d112bcaafb14ddcb8dd7d47f Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2765676 Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
332 lines
9.9 KiB
C
332 lines
9.9 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra_hwpm_mem_mgmt.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_internal.h>
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#include <hal/t234/hw/t234_pmasys_soc_hwpm.h>
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#include <hal/t234/hw/t234_pmmsys_soc_hwpm.h>
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int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outbase_r(0), 0);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outbaseupper_r(0), 0);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outsize_r(0), 0);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_mem_bytes_addr_r(0), 0);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 outbase_lo = 0;
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u32 outbase_hi = 0;
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u32 outsize = 0;
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u64 mem_bytes_addr = 0ULL;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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struct tegra_hwpm_mem_mgmt *mem_mgmt = hwpm->mem_mgmt;
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tegra_hwpm_fn(hwpm, " ");
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outbase_lo = mem_mgmt->stream_buf_va & pmasys_channel_outbase_ptr_m();
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outbase_r(0), outbase_lo);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASE = 0x%x", outbase_lo);
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outbase_hi = (mem_mgmt->stream_buf_va >> 32) &
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pmasys_channel_outbaseupper_ptr_m();
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outbaseupper_r(0), outbase_hi);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTBASEUPPER = 0x%x", outbase_hi);
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outsize = mem_mgmt->stream_buf_size &
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pmasys_channel_outsize_numbytes_m();
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_outsize_r(0), outsize);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose, "OUTSIZE = 0x%x", outsize);
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mem_bytes_addr = mem_mgmt->mem_bytes_buf_va &
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pmasys_channel_mem_bytes_addr_ptr_m();
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_mem_bytes_addr_r(0), mem_bytes_addr);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose,
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"MEM_BYTES_ADDR = 0x%llx", mem_bytes_addr);
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_mem_block_r(0),
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pmasys_channel_mem_block_valid_f(
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pmasys_channel_mem_block_valid_true_v()));
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_writel(hwpm, pma_perfmux, pmasys_channel_mem_block_r(0),
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pmasys_channel_mem_block_valid_f(
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pmasys_channel_mem_block_valid_false_v()));
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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u32 *mem_bytes_kernel_u32 =
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(u32 *)(hwpm->mem_mgmt->mem_bytes_kernel);
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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*mem_bytes_kernel_u32 = TEGRA_HWPM_MEM_BYTES_INVALID;
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err = tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_control_user_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val,
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pmasys_channel_control_user_update_bytes_m(),
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pmasys_channel_control_user_update_bytes_doit_f());
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_control_user_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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/* Disable PMA streaming */
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err = tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_trigger_config_user_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val,
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pmasys_trigger_config_user_record_stream_m(),
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pmasys_trigger_config_user_record_stream_disable_f());
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_trigger_config_user_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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err = tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_control_user_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val,
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pmasys_channel_control_user_stream_m(),
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pmasys_channel_control_user_stream_disable_f());
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_control_user_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
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u64 mem_bump)
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{
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int err = 0;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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if (mem_bump > (u64)U32_MAX) {
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tegra_hwpm_err(hwpm, "mem_bump is out of bounds");
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return -EINVAL;
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}
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err = tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_mem_bump_r(0), mem_bump);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_mem_head_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return 0ULL;
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}
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return (u64)reg_val;
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}
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bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val, field_val;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx(hwpm)];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T234_HWPM_IP_RTR_STATIC_PMA_INST];
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struct hwpm_ip_aperture *pma_perfmux = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T234_HWPM_IP_RTR_PERMUX_INDEX];
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tegra_hwpm_fn(hwpm, " ");
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err = tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_status_secure_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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field_val = pmasys_channel_status_secure_membuf_status_v(
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reg_val);
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return (field_val ==
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pmasys_channel_status_secure_membuf_status_overflowed_v());
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}
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