mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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2f26b5849e
This patch adds support for MCF SOC performance monitoring in the driver. MCF SOC has two different types of perfmuxes connected to the same perfmon: one is the OCU type and the other is IBHX and OBHX. IBHX is only accessible via MC16 aperture. Therefore, this patch adds two separate IPs: OCU and IOBHX. However, both are tied to the MCF SOC perfmon (mcfsoc0). Bug 4287384 Signed-off-by: Vishal Aslot <vaslot@nvidia.com> Change-Id: If15498a44e02270f9106337078931edbe043c254 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2986232 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
444 lines
13 KiB
C
444 lines
13 KiB
C
// SPDX-License-Identifier: MIT
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/* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_soc.h>
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_static_analysis.h>
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#include <hal/th500/th500_internal.h>
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#include <hal/th500/soc/th500_soc_internal.h>
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#include <hal/th500/soc/hw/th500_addr_map_soc_hwpm.h>
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/*
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* This function is invoked by register_ip API.
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* Convert the external resource enum to internal IP index.
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* Extract given ip_ops and update corresponding IP structure.
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*/
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int th500_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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u32 resource_enum, u64 base_address,
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struct tegra_hwpm_ip_ops *ip_ops, bool available)
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{
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int ret = 0;
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u32 ip_idx = 0U;
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"Extract IP ops for resource enum %d info", resource_enum);
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/* Convert tegra_soc_hwpm_resource to internal enum */
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if (!(hwpm->active_chip->is_resource_active(hwpm,
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resource_enum, &ip_idx))) {
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"SOC hwpm resource %d (base 0x%llx) is unconfigured",
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resource_enum, base_address);
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goto fail;
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}
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switch (ip_idx) {
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#if defined(CONFIG_TH500_HWPM_IP_CL2)
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case TH500_HWPM_IP_CL2:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_SMMU)
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case TH500_HWPM_IP_SMMU:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
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case TH500_HWPM_IP_NVLCTRL:
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case TH500_HWPM_IP_NVLRX:
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case TH500_HWPM_IP_NVLTX:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_PCIE)
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case TH500_HWPM_IP_PCIE:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C2C)
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case TH500_HWPM_IP_C2C:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_CL2) || \
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defined(CONFIG_TH500_HWPM_IP_SMMU) || \
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defined(CONFIG_TH500_HWPM_IP_C_NVLINK) || \
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defined(CONFIG_TH500_HWPM_IP_PCIE) || \
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defined(CONFIG_TH500_HWPM_IP_C2C)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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case TH500_HWPM_IP_MSS_CHANNEL:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
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case TH500_HWPM_IP_MSS_HUB:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
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case TH500_HWPM_IP_MCF_CORE:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
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case TH500_HWPM_IP_MCF_CLINK:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
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case TH500_HWPM_IP_MCF_C2C:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU)
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case TH500_HWPM_IP_MCF_OCU:
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX)
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case TH500_HWPM_IP_MCF_IOBHX:
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#endif
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/*
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* MSS channel, MCF CORE, MCF CLINK, MCF C2C, MCF SOC,
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* and MSS HUB share MC channels
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*/
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/* Check base address in TH500_HWPM_IP_MSS_CHANNEL */
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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ip_idx = TH500_HWPM_IP_MSS_CHANNEL;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
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/* Check base address in TH500_HWPM_IP_MCF_CORE */
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ip_idx = TH500_HWPM_IP_MCF_CORE;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
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/* Check base address in TH500_HWPM_IP_MCF_CLINK */
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ip_idx = TH500_HWPM_IP_MCF_CLINK;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
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/* Check base address in TH500_HWPM_IP_MCF_C2C */
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ip_idx = TH500_HWPM_IP_MCF_C2C;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_OCU)
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/* Check base address in TH500_HWPM_IP_MCF_OCU */
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ip_idx = TH500_HWPM_IP_MCF_OCU;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_IOBHX)
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/* Check base address in TH500_HWPM_IP_MCF_IOBHX */
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ip_idx = TH500_HWPM_IP_MCF_IOBHX;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
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/* Check base address in TH500_HWPM_IP_MSS_HUB */
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ip_idx = TH500_HWPM_IP_MSS_HUB;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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break;
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case TH500_HWPM_IP_PMA:
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case TH500_HWPM_IP_RTR:
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default:
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tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx);
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break;
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}
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fail:
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return ret;
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}
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int th500_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
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{
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u32 production_mode = 0U;
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u32 security_mode = 0U;
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u32 fa_mode = 0U;
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u32 hwpm_global_disable = 0U;
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u32 opt_hwpm_disable = 0U;
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u32 idx = 0U;
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int err;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = NULL;
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tegra_hwpm_fn(hwpm, " ");
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if (!tegra_hwpm_is_platform_silicon()) {
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return 0;
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}
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/* Read production mode fuse */
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err = tegra_hwpm_fuse_readl_prod_mode(hwpm, &production_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "prod mode fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_SECURITY_MODE 0xA0U
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err = tegra_hwpm_fuse_readl(
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hwpm, TEGRA_FUSE_SECURITY_MODE, &security_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "security mode fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_OPT_HWPM_DISABLE 0x2cU
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err = tegra_hwpm_fuse_readl(
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hwpm, TEGRA_FUSE_SECURITY_MODE, &opt_hwpm_disable);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "opt hwpm disable fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_FA_MODE 0x48U
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err = tegra_hwpm_fuse_readl(hwpm, TEGRA_FUSE_FA_MODE, &fa_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "fa mode fuse read failed");
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return err;
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}
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#define TEGRA_HWPM_GLOBAL_DISABLE_OFFSET 0x3CU
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#define TEGRA_HWPM_GLOBAL_DISABLE_DISABLED 0x1U
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err = tegra_hwpm_read_sticky_bits(hwpm, addr_map_pmc_misc_base_r(),
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TEGRA_HWPM_GLOBAL_DISABLE_OFFSET, &hwpm_global_disable);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm global disable read failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"PROD_MODE fuse = 0x%x "
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"SECURITY_MODE fuse = 0x%x "
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"HWPM disable fuse = 0x%x"
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"FA mode fuse = 0x%x"
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"HWPM_GLOBAL_DISABLE sticky bit = 0x%x",
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production_mode, security_mode, opt_hwpm_disable,
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fa_mode, hwpm_global_disable);
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/* Do not enable override if FA mode fuse is set */
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if (fa_mode != 0U) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"fa mode fuse enabled, no override required");
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return 0;
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}
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/* Override enable depends on security mode and global hwpm disable */
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if ((security_mode == 0U) &&
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(hwpm_global_disable == TEGRA_HWPM_GLOBAL_DISABLE_DISABLED)) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"security fuses are disabled, no override required");
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return 0;
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}
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for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) {
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chip_ip = active_chip->chip_ips[idx];
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if ((hwpm_global_disable !=
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TEGRA_HWPM_GLOBAL_DISABLE_DISABLED) &&
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((chip_ip->dependent_fuse_mask &
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TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK) != 0U)) {
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/* HWPM disable is true */
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/* IP depends on HWPM global disable */
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chip_ip->override_enable = true;
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} else {
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/* HWPM disable is false */
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if ((security_mode != 0U) &&
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((chip_ip->dependent_fuse_mask &
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TEGRA_HWPM_FUSE_SECURITY_MODE_MASK) != 0U)) {
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/* Security mode fuse is set */
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/* IP depends on security mode fuse */
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chip_ip->override_enable = true;
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} else {
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/*
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* This is a valid case since not all IPs
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* depend on security fuse.
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*/
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"IP %d not overridden", idx);
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}
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}
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}
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return 0;
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}
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int th500_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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{
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int ret = 0, err = 0;
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tegra_hwpm_fn(hwpm, " ");
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#if defined(CONFIG_TH500_HWPM_ALLOW_FORCE_ENABLE)
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/* MSS CHANNEL */
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mc0_base_r(), TH500_HWPM_IP_MSS_CHANNEL, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"TH500_HWPM_IP_MSS_CHANNEL force enable failed");
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err = ret;
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}
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C2C)
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/* CTC Link */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_c2c0_base_r(), TH500_HWPM_IP_C2C, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"TH500_HWPM_IP_C2C force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_c2c5_base_r(), TH500_HWPM_IP_C2C, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"TH500_HWPM_IP_C2C force enable failed");
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return ret;
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}
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#endif
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#endif
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return err;
|
|
}
|