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da3bda1364
- HALs get_rtr_int_idx and get_ip_max_idx return the chip specific router index and number of IPs. This information is static for a chip and doesn't require any input. Hence, update the HAL definition to not require hwpm pointer as an argument. Update definition and references for these HALs. - Add new HAL to get PMA and RTR structure pointers. Implement and update other chip specific functions to use new HAL. - Add new timer macro to check a condition and timeout after given retries. Update necessary code to use new timer macro. - Correct validate_emc_config function to compute correct available mss channel mask based on fuse value. - Update tegra_hwpm_readl and tegra_hwpm_writel macros to assert error value. This way error checks are added at one spot and not sprinkled all over the driver code. - Update get_mem_bytes_put_ptr() and membuf_overflow_status() to return error as function return and accept arguments to return mem_head pointer and overflow status respectively. Add overflow status macros to use throughout driver. Update HAL definition and references accordingly. - conftest is only compiled for OOT config atm. Add OOT config check to include conftest header. Jira THWPM-109 Change-Id: I77d150e860fa344a1604d241e27718150fdb8647 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2982555 Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Vishal Aslot <vaslot@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
99 lines
3.4 KiB
C
99 lines
3.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TEGRA_HWPM_IO_H
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#define TEGRA_HWPM_IO_H
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#include <tegra_hwpm_types.h>
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#include <tegra_hwpm_log.h>
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/**
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* Sets a particular field value in input data.
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*
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* Uses mask to clear specific bit positions in curr_val. field_val
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* is used to set the bits in curr_val to be returned.
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* Note: Function does not perform any validation of input parameters.
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*
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* curr_val [in] Current input data value.
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*
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* mask [in] Mask of the bits to be updated.
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*
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* field_val [in] Value to change the mask bits to.
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*
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* Returns updated value.
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*/
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static inline u32 set_field(u32 curr_val, u32 mask, u32 field_val)
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{
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return ((curr_val & ~mask) | field_val);
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}
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/**
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* Retrieve value of specific bits from input data.
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* Note: Function does not perform any validation of input parameters.
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*
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* input_data [in] Data to retrieve value from.
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*
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* mask [in] Mask of the bits to get value from.
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*
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* Return value from input_data corresponding to mask bits.
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*/
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static inline u32 get_field(u32 input_data, u32 mask)
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{
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return (input_data & mask);
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}
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#ifdef __KERNEL__
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#include <os/linux/io_utils.h>
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#else
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#include <os/qnx/io_utils.h>
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#endif
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#define tegra_hwpm_read_sticky_bits(hwpm, reg_base, reg_offset, val) \
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tegra_hwpm_read_sticky_bits_impl(hwpm, reg_base, reg_offset, val)
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#define tegra_hwpm_fake_readl(hwpm, aperture, addr, val) \
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tegra_hwpm_fake_readl_impl(hwpm, aperture, addr, val)
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#define tegra_hwpm_fake_writel(hwpm, aperture, addr, val) \
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tegra_hwpm_fake_writel_impl(hwpm, aperture, addr, val)
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#define tegra_hwpm_readl(hwpm, aperture, addr, val) ({ \
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int err = tegra_hwpm_readl_impl(hwpm, aperture, addr, val); \
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hwpm_assert_print(hwpm, err == 0, return err, \
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"hwpm read addr 0x%lx failed", (u64)addr); \
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})
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#define tegra_hwpm_writel(hwpm, aperture, addr, val)({ \
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int err = tegra_hwpm_writel_impl(hwpm, aperture, addr, val); \
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hwpm_assert_print(hwpm, err == 0, return err, \
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"hwpm write addr 0x%lx failed", (u64)addr); \
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})
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#define tegra_hwpm_regops_readl(hwpm, ip_inst, aperture, addr, val) \
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tegra_hwpm_regops_readl_impl(hwpm, ip_inst, aperture, addr, val)
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#define tegra_hwpm_regops_writel(hwpm, ip_inst, aperture, addr, val) \
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tegra_hwpm_regops_writel_impl(hwpm, ip_inst, aperture, addr, val)
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#endif /* TEGRA_HWPM_IO_H */
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