mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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3edf3f6034
Move chip specific code to chip specific folder. This will allow multiple chip support in the future. Create new specific functions - Initialize hwpm structures - Reserve and release PMA and RTR apertures - Zero, update and check allowlists - Set and get fake registers for MC aperture on simulation - perfmon dt aperture enums Jira THWPM-41 Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
150 lines
3.8 KiB
C
150 lines
3.8 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_SOC_HWPM_STRUCTURES_H
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#define TEGRA_SOC_HWPM_STRUCTURES_H
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/cdev.h>
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#include <linux/delay.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#define TEGRA_SOC_HWPM_DT_APERTURE_INVALID 100U
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#define RELEASE_FAIL(msg, ...) \
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do { \
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if (err < 0) { \
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tegra_soc_hwpm_err(msg, ##__VA_ARGS__); \
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if (ret == 0) \
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ret = err; \
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} \
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} while (0)
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/* FIXME: Default timeout is 1 sec. Is this sufficient for pre-si? */
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#define HWPM_TIMEOUT(timeout_check, expiry_msg) ({ \
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bool timeout_expired = false; \
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s32 timeout_msecs = 1000; \
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u32 sleep_msecs = 100; \
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while (!(timeout_check)) { \
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msleep(sleep_msecs); \
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timeout_msecs -= sleep_msecs; \
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if (timeout_msecs <= 0) { \
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tegra_soc_hwpm_err("Timeout expired for %s!", \
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expiry_msg); \
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timeout_expired = true; \
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break; \
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} \
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} \
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timeout_expired; \
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})
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struct allowlist;
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extern struct platform_device *tegra_soc_hwpm_pdev;
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extern const struct file_operations tegra_soc_hwpm_ops;
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/* Driver struct */
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struct tegra_soc_hwpm {
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/* Device */
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struct platform_device *pdev;
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struct device *dev;
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struct device_node *np;
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struct class class;
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dev_t dev_t;
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struct cdev cdev;
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struct hwpm_resource *hwpm_resources;
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/* IP floorsweep info */
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u64 ip_fs_info[TERGA_SOC_HWPM_NUM_IPS];
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/* MMIO apertures in device tree */
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void __iomem **dt_apertures;
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/* Clocks and resets */
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struct clk *la_clk;
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struct clk *la_parent_clk;
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struct reset_control *la_rst;
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struct reset_control *hwpm_rst;
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struct tegra_soc_hwpm_ip_ops *ip_info;
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/* Memory Management */
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struct dma_buf *stream_dma_buf;
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struct dma_buf_attachment *stream_attach;
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struct sg_table *stream_sgt;
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struct dma_buf *mem_bytes_dma_buf;
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struct dma_buf_attachment *mem_bytes_attach;
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struct sg_table *mem_bytes_sgt;
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void *mem_bytes_kernel;
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/* SW State */
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bool bind_completed;
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s32 full_alist_size;
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/* Debugging */
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#ifdef CONFIG_DEBUG_FS
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struct dentry *debugfs_root;
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#endif
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bool fake_registers_enabled;
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};
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struct hwpm_resource_aperture {
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/*
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* If false, this is a HWPM aperture (PERFRMON, PMA or RTR). Else this
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* is a non-HWPM aperture (ex: VIC).
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*/
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bool is_ip;
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/*
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* If is_ip == false, specify dt_aperture for readl/writel operations.
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* If is_ip == true, dt_aperture == TEGRA_SOC_HWPM_INVALID_DT.
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*/
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u32 dt_aperture;
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/* Physical aperture */
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u64 start_abs_pa;
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u64 end_abs_pa;
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u64 start_pa;
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u64 end_pa;
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/* Allowlist */
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struct allowlist *alist;
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u64 alist_size;
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/*
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* Currently, perfmons and perfmuxes for all instances of an IP
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* are listed in a single aperture mask. It is possible that
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* some instances are disable. In this case, accessing corresponding
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* registers will result in kernel panic.
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* Bit set in the index_mask value will indicate the instance index
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* within that IP (or resource).
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*/
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u32 index_mask;
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/* Fake registers for VDK which doesn't have a SOC HWPM fmodel */
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u32 *fake_registers;
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};
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struct hwpm_resource {
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bool reserved;
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u32 map_size;
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struct hwpm_resource_aperture *map;
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};
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#endif /* TEGRA_SOC_HWPM_STRUCTURES_H */
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