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git://nv-tegra.nvidia.com/linux-hwpm.git
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3edf3f6034
Move chip specific code to chip specific folder. This will allow multiple chip support in the future. Create new specific functions - Initialize hwpm structures - Reserve and release PMA and RTR apertures - Zero, update and check allowlists - Set and get fake registers for MC aperture on simulation - perfmon dt aperture enums Jira THWPM-41 Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
56 lines
1.8 KiB
C
56 lines
1.8 KiB
C
/*
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* tegra-soc-hwpm-io.h:
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* This header defines register read/write APIs for the Tegra SOC HWPM driver.
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_SOC_HWPM_IO_H
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#define TEGRA_SOC_HWPM_IO_H
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struct tegra_soc_hwpm;
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struct hwpm_resource_aperture;
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struct hwpm_resource_aperture *find_hwpm_aperture(struct tegra_soc_hwpm *hwpm,
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u64 phys_addr,
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bool use_absolute_base,
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bool check_reservation,
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u64 *updated_pa);
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u32 hwpm_readl(struct tegra_soc_hwpm *hwpm,
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u32 dt_aperture,
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u32 reg_offset);
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void hwpm_writel(struct tegra_soc_hwpm *hwpm,
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u32 dt_aperture,
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u32 reg_offset, u32 val);
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u32 ip_readl(struct tegra_soc_hwpm *hwpm, u64 phys_addr);
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void ip_writel(struct tegra_soc_hwpm *hwpm, u64 phys_addr, u32 val);
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u32 ioctl_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr);
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void ioctl_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u64 addr,
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u32 val);
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int reg_rmw(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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u32 dt_aperture,
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u64 addr,
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u32 field_mask,
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u32 field_val,
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bool is_ioctl,
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bool is_ip);
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#endif /* TEGRA_SOC_HWPM_IO_H */
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