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474df3d0b4
ISP is part of Camera IP. Add IP files to enable ISP IP. Jira THWPM-90 Bug 4345706 Signed-off-by: vasukis <vasukis@nvidia.com> Change-Id: I2458181b89234bcf50a674de7697dc961407922d Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3263621 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Yifei Wan <ywan@nvidia.com>
654 lines
19 KiB
C
654 lines
19 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm_static_analysis.h>
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_soc.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t264/t264_internal.h>
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#include <hal/t264/hw/t264_addr_map_soc_hwpm.h>
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/*
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* This function is invoked by register_ip API.
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* Convert the external resource enum to internal IP index.
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* Extract given ip_ops and update corresponding IP structure.
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*/
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int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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u32 resource_enum, u64 base_address,
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struct tegra_hwpm_ip_ops *ip_ops, bool available)
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{
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int ret = 0;
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u32 ip_idx = 0U;
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"Extract IP ops for resource enum %d info", resource_enum);
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/* Convert tegra_soc_hwpm_resource to internal enum */
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if (!(t264_hwpm_is_resource_active(hwpm, resource_enum, &ip_idx))) {
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tegra_hwpm_err(hwpm,
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"SOC hwpm resource %d (base 0x%llx) is unconfigured",
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resource_enum, (unsigned long long)base_address);
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goto fail;
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}
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switch (ip_idx) {
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#if defined(CONFIG_T264_HWPM_IP_VIC)
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case T264_HWPM_IP_VIC:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_PVA)
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case T264_HWPM_IP_PVA:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_OCU)
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case T264_HWPM_IP_OCU:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_SMMU)
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case T264_HWPM_IP_SMMU:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_UCF_MSW)
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case T264_HWPM_IP_UCF_MSW:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_UCF_PSW)
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case T264_HWPM_IP_UCF_PSW:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_UCF_CSW)
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case T264_HWPM_IP_UCF_CSW:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_CPU)
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case T264_HWPM_IP_CPU:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_VI)
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case T264_HWPM_IP_VI:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_ISP)
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case T264_HWPM_IP_ISP:
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#endif
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Failed to %s fs/ops for IP %d (base 0x%llx)",
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available == true ? "set" : "reset",
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ip_idx, (unsigned long long)base_address);
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goto fail;
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}
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break;
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#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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case T264_HWPM_IP_MSS_CHANNEL:
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#endif
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#if defined(CONFIG_T264_HWPM_IP_MSS_HUBS)
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case T264_HWPM_IP_MSS_HUBS:
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#endif
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/* MSS channel and MSS hubs share MC channels */
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/* Check base address in T264_HWPM_IP_MSS_CHANNEL */
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#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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ip_idx = T264_HWPM_IP_MSS_CHANNEL;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, (unsigned long long)base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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/*
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* ret = -ENODEV indicates given address doesn't belong
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* to IP. This means ip_ops will not be set for this IP.
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* This shouldn't be a reason to fail this function.
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* Hence, reset ret to 0.
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*/
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ret = 0;
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}
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#endif
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/* Check base address in T264_HWPM_IP_MSS_HUBS */
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#if defined(CONFIG_T264_HWPM_IP_MSS_HUBS)
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ip_idx = T264_HWPM_IP_MSS_HUBS;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, (unsigned long long)base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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/*
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* ret = -ENODEV indicates given address doesn't belong
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* to IP. This means ip_ops will not be set for this IP.
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* This shouldn't be a reason to fail this function.
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* Hence, reset ret to 0.
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*/
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ret = 0;
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}
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#endif
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break;
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case T264_HWPM_IP_PMA:
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case T264_HWPM_IP_RTR:
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default:
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tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx);
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break;
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}
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fail:
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return ret;
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}
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static int t264_hwpm_validate_emc_config(struct tegra_soc_hwpm *hwpm)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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# if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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struct hwpm_ip *chip_ip = NULL;
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struct hwpm_ip_inst *ip_inst = NULL;
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u32 inst_idx = 0U;
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u32 element_mask_max = 0U;
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#endif
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u32 mss_disable_fuse_val = 0U;
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u32 mss_disable_fuse_val_mask = 0xFU;
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u32 mss_disable_fuse_bit_idx = 0U;
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u32 emc_element_floorsweep_mask = 0U;
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u32 idx = 0U;
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int err;
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tegra_hwpm_fn(hwpm, " ");
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if (!tegra_hwpm_is_platform_silicon()) {
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tegra_hwpm_err(hwpm,
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"Fuse readl is not implemented yet. Skip for now ");
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return 0;
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}
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#define TEGRA_FUSE_OPT_MSS_DISABLE 0x8c0U
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err = tegra_hwpm_fuse_readl(hwpm,
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TEGRA_FUSE_OPT_MSS_DISABLE, &mss_disable_fuse_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "emc_disable fuse read failed");
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return err;
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}
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/*
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* In floorsweep fuse value,
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* each bit corresponds to 4 elements.
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* Bit value 0 indicates those elements are
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* available and bit value 1 indicates
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* corresponding elements are floorswept.
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*
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* Convert floorsweep fuse value to available EMC elements.
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*/
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do {
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if (!(mss_disable_fuse_val & (0x1U << mss_disable_fuse_bit_idx))) {
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emc_element_floorsweep_mask |=
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(0xFU << (mss_disable_fuse_bit_idx * 4U));
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}
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mss_disable_fuse_bit_idx++;
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mss_disable_fuse_val_mask = (mss_disable_fuse_val_mask >> 1U);
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} while (mss_disable_fuse_val_mask != 0U);
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/* Set fuse value in MSS IP instances */
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for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) {
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switch (idx) {
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#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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case T264_HWPM_IP_MSS_CHANNEL:
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#endif
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# if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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chip_ip = active_chip->chip_ips[idx];
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for (inst_idx = 0U; inst_idx < chip_ip->num_instances;
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inst_idx++) {
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ip_inst = &chip_ip->ip_inst_static_array[
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inst_idx];
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/*
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* Hence use max element mask to get correct
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* fs info to use in HWPM driver.
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*/
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element_mask_max = tegra_hwpm_safe_sub_u32(
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tegra_hwpm_safe_cast_u64_to_u32(BIT(
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ip_inst->num_core_elements_per_inst)),
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1U);
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ip_inst->fuse_fs_mask =
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(emc_element_floorsweep_mask &
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element_mask_max);
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"ip %d, fuse_mask 0x%x",
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idx, ip_inst->fuse_fs_mask);
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}
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break;
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#endif
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default:
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continue;
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}
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}
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return 0;
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}
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int t264_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
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{
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u32 opt_hwpm_disable = 0U;
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u32 fa_mode = 0U;
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u32 hwpm_global_disable = 0U;
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u32 idx = 0U;
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int err;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = NULL;
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tegra_hwpm_fn(hwpm, " ");
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if (!tegra_hwpm_is_platform_silicon()) {
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return 0;
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}
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err = t264_hwpm_validate_emc_config(hwpm);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to validate emc config");
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return err;
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}
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#define TEGRA_FUSE_OPT_HWPM_DISABLE 0xc18
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/* Read fuse_opt_hwpm_disable_0 fuse */
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err = tegra_hwpm_fuse_readl(hwpm,
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TEGRA_FUSE_OPT_HWPM_DISABLE, &opt_hwpm_disable);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "opt_hwpm_disable fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_FA_MODE 0x48U
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err = tegra_hwpm_fuse_readl(hwpm, TEGRA_FUSE_FA_MODE, &fa_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "fa mode fuse read failed");
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return err;
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}
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/*
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* Configure global control register to disable PCFIFO interlock
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* By writing to MSS_HUB_HUBC_CONFIG_0 register
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*/
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#define TEGRA_HUB_HUBC_CONFIG0_OFFSET 0x6244U
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#define TEGRA_HUB_HUBC_PCFIFO_INTERLOCK_DISABLED 0x1U
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err = tegra_hwpm_write_sticky_bits(hwpm, addr_map_mcb_base_r(),
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TEGRA_HUB_HUBC_CONFIG0_OFFSET,
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TEGRA_HUB_HUBC_PCFIFO_INTERLOCK_DISABLED);
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hwpm_assert_print(hwpm, err == 0, return err,
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"PCFIFO Interlock disable failed");
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#define TEGRA_HWPM_GLOBAL_DISABLE_OFFSET 0x300CU
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#define TEGRA_HWPM_GLOBAL_DISABLE_DISABLED 0x0U
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err = tegra_hwpm_read_sticky_bits(hwpm, addr_map_pmc_misc_base_r(),
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TEGRA_HWPM_GLOBAL_DISABLE_OFFSET, &hwpm_global_disable);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm global disable read failed");
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return err;
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}
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/*
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* Do not enable override if FA mode fuse is set. FA_MODE fuse enables
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* all PERFMONs regardless of level of fuse, sticky bit or secure register
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* settings.
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*/
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if (fa_mode != 0U) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"fa mode fuse enabled, no override required, enable HWPM");
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return 0;
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}
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/* Override enable depends on opt_hwpm_disable and global hwpm disable */
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if ((opt_hwpm_disable == 0U) &&
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(hwpm_global_disable == TEGRA_HWPM_GLOBAL_DISABLE_DISABLED)) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"OPT_HWPM_DISABLE fuses are disabled, no override required");
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return 0;
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}
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for (idx = 0U; idx < active_chip->get_ip_max_idx(); idx++) {
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chip_ip = active_chip->chip_ips[idx];
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if ((hwpm_global_disable !=
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TEGRA_HWPM_GLOBAL_DISABLE_DISABLED) ||
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(opt_hwpm_disable != 0U)) {
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/*
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* Both HWPM_GLOBAL_DISABLE and OPT_HWPM_DISABLE disables all
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* Perfmons in SOC HWPM. Hence, check for either of them to be set.
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*/
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if ((chip_ip->dependent_fuse_mask &
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TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK) != 0U) {
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/*
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* check to prevent RTR from being overriden
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*/
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chip_ip->override_enable = true;
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} else {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"IP %d not overridden", idx);
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}
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}
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}
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return 0;
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}
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int t264_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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{
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int ret = 0;
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tegra_hwpm_fn(hwpm, " ");
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/* Force enable MSS channel IP for AV+L/Q */
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if (tegra_hwpm_is_hypervisor_mode()) {
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/*
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* MSS CHANNEL
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* MSS channel driver cannot implement HWPM <-> IP interface in AV + L, and
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* AV + Q configs. Since MSS channel is part of both POR and non-POR IPs,
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* this force enable is not limited by minimal config or force enable flags.
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*/
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#if defined(CONFIG_T264_HWPM_IP_MSS_CHANNEL)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mc0_base_r(),
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T264_HWPM_IP_MSS_CHANNEL, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_MSS_CHANNEL force enable failed");
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return ret;
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}
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#endif
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} else {
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#if defined(CONFIG_T264_HWPM_ALLOW_FORCE_ENABLE)
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if (tegra_hwpm_is_platform_vsp()) {
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/* Static IP instances as per VSP netlist */
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}
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if (tegra_hwpm_is_platform_silicon()) {
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/* Static IP instances corresponding to silicon */
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#if defined(CONFIG_T264_HWPM_IP_OCU)
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if (hwpm->ip_config[TEGRA_HWPM_IP_MCF_OCU]) {
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_ocu_base_r(),
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T264_HWPM_IP_OCU, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_OCU force enable failed");
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return ret;
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}
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}
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#endif
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#if defined(CONFIG_T264_HWPM_IP_UCF_PSW)
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if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_PSW]) {
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_ucf_psn0_psw_base_r(),
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T264_HWPM_IP_UCF_PSW, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_UCF_PSW force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_ucf_psn1_psw_base_r(),
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T264_HWPM_IP_UCF_PSW, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_UCF_PSW force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_ucf_psn2_psw_base_r(),
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T264_HWPM_IP_UCF_PSW, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_UCF_PSW force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_ucf_psn3_psw_base_r(),
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T264_HWPM_IP_UCF_PSW, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T264_HWPM_IP_UCF_PSW force enable failed");
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return ret;
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}
|
|
}
|
|
#endif /* CONFIG_T264_HWPM_IP_UCF_PSW */
|
|
#if defined(CONFIG_T264_HWPM_IP_UCF_CSW)
|
|
if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_CSW]) {
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_ucf_csw0_base_r(),
|
|
T264_HWPM_IP_UCF_CSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_CSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_ucf_csw1_base_r(),
|
|
T264_HWPM_IP_UCF_CSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_CSW force enable failed");
|
|
return ret;
|
|
}
|
|
}
|
|
#endif /* CONFIG_T264_HWPM_IP_UCF_CSW */
|
|
#if defined(CONFIG_T264_HWPM_IP_UCF_MSW)
|
|
if (hwpm->ip_config[TEGRA_HWPM_IP_UCF_MSW]) {
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc0_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc2_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc4_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc6_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc8_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc10_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc12_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_mc14_base_r(),
|
|
T264_HWPM_IP_UCF_MSW, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_UCF_MSW force enable failed");
|
|
return ret;
|
|
}
|
|
}
|
|
#endif /* CONFIG_T264_HWPM_IP_UCF_MSW */
|
|
#if defined(CONFIG_T264_HWPM_IP_CPU)
|
|
if (hwpm->ip_config[TEGRA_HWPM_IP_CPU]) {
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore0_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore1_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore2_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore3_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore4_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore5_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore6_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore7_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore8_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore9_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore10_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore11_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore12_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
|
|
addr_map_cpucore13_base_r(),
|
|
T264_HWPM_IP_CPU, true);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm,
|
|
"T264_HWPM_IP_CPU force enable failed");
|
|
return ret;
|
|
}
|
|
}
|
|
#endif /* CONFIG_T264_HWPM_IP_CPU */
|
|
}
|
|
#endif /* CONFIG_T264_HWPM_ALLOW_FORCE_ENABLE */
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|