mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-24 10:13:00 +03:00
486ec4a24c
Stream and allowlist buffers are allocated by the user as dma buffers and mapped in virtual address space by the driver. The DMA and mapping functions are linux specific. Hence create memory management and allowlist linux structures. Add these linux memory structure pointers in the tegra_hwpm parent structure. Jira THWPM-60 Change-Id: I2526f2bab835df4c5a922b0b375c22a6247aad30 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2729664 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
518 lines
13 KiB
C
518 lines
13 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_static_analysis.h>
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#include <hal/t234/t234_internal.h>
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#include <hal/t234/hw/t234_addr_map_soc_hwpm.h>
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/*
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* This function is invoked by register_ip API.
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* Convert the external resource enum to internal IP index.
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* Extract given ip_ops and update corresponding IP structure.
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*/
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int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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u32 resource_enum, u64 base_address,
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struct tegra_hwpm_ip_ops *ip_ops, bool available)
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{
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int ret = 0;
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u32 ip_idx = 0U;
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"Extract IP ops for resource enum %d info", resource_enum);
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/* Convert tegra_soc_hwpm_resource to internal enum */
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if (!(t234_hwpm_is_resource_active(hwpm, resource_enum, &ip_idx))) {
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tegra_hwpm_dbg(hwpm, hwpm_dbg_ip_register,
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"SOC hwpm resource %d (base 0x%llx) is unconfigured",
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resource_enum, base_address);
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goto fail;
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}
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switch (ip_idx) {
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#if defined(CONFIG_T234_HWPM_IP_VI)
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case T234_HWPM_IP_VI:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_ISP)
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case T234_HWPM_IP_ISP:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_VIC)
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case T234_HWPM_IP_VIC:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_OFA)
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case T234_HWPM_IP_OFA:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_PVA)
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case T234_HWPM_IP_PVA:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_NVDLA)
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case T234_HWPM_IP_NVDLA:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MGBE)
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case T234_HWPM_IP_MGBE:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_SCF)
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case T234_HWPM_IP_SCF:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_NVDEC)
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case T234_HWPM_IP_NVDEC:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_NVENC)
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case T234_HWPM_IP_NVENC:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_PCIE)
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case T234_HWPM_IP_PCIE:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_DISPLAY)
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case T234_HWPM_IP_DISPLAY:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
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case T234_HWPM_IP_MSS_GPU_HUB:
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#endif
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Failed to %s fs/ops for IP %d (base 0x%llx)",
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available == true ? "set" : "reset",
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ip_idx, base_address);
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goto fail;
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}
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break;
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#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
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case T234_HWPM_IP_MSS_CHANNEL:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_ISO_NISO_HUBS)
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case T234_HWPM_IP_MSS_ISO_NISO_HUBS:
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_MCF)
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case T234_HWPM_IP_MSS_MCF:
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#endif
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/* MSS channel, ISO NISO hubs and MCF share MC channels */
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/* Check base address in T234_HWPM_IP_MSS_CHANNEL */
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#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
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ip_idx = T234_HWPM_IP_MSS_CHANNEL;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_ISO_NISO_HUBS)
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/* Check base address in T234_HWPM_IP_MSS_ISO_NISO_HUBS */
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ip_idx = T234_HWPM_IP_MSS_ISO_NISO_HUBS;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_MCF)
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/* Check base address in T234_HWPM_IP_MSS_MCF */
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ip_idx = T234_HWPM_IP_MSS_MCF;
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, ip_ops,
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base_address, ip_idx, available);
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if (ret != 0) {
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/*
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* Return value of ENODEV will indicate that the base
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* address doesn't belong to this IP.
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* This case is valid, as not all base addresses are
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* shared between MSS IPs.
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* In this case, reset return value to 0.
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*/
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if (ret != -ENODEV) {
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tegra_hwpm_err(hwpm,
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"IP %d base 0x%llx:Failed to %s fs/ops",
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ip_idx, base_address,
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available == true ? "set" : "reset");
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goto fail;
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}
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ret = 0;
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}
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#endif
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break;
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case T234_HWPM_IP_PMA:
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case T234_HWPM_IP_RTR:
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default:
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tegra_hwpm_err(hwpm, "Invalid IP %d for ip_ops", ip_idx);
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break;
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}
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fail:
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return ret;
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}
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int t234_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm)
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{
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u32 production_mode = 0U;
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u32 security_mode = 0U;
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u32 fa_mode = 0U;
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u32 hwpm_global_disable = 0U;
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u32 idx = 0U;
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int err;
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = NULL;
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tegra_hwpm_fn(hwpm, " ");
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if (!tegra_platform_is_silicon()) {
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return 0;
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}
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/* Read production mode fuse */
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err = tegra_fuse_readl(TEGRA_FUSE_PRODUCTION_MODE, &production_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "prod mode fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_SECURITY_MODE 0xA0U
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err = tegra_fuse_readl(TEGRA_FUSE_SECURITY_MODE, &security_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "security mode fuse read failed");
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return err;
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}
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#define TEGRA_FUSE_FA_MODE 0x48U
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err = tegra_fuse_readl(TEGRA_FUSE_FA_MODE, &fa_mode);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "fa mode fuse read failed");
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return err;
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}
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#define TEGRA_HWPM_GLOBAL_DISABLE_OFFSET 0x3CU
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#define TEGRA_HWPM_GLOBAL_DISABLE_DISABLED 0x0U
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err = tegra_hwpm_read_sticky_bits(hwpm, addr_map_pmc_misc_base_r(),
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TEGRA_HWPM_GLOBAL_DISABLE_OFFSET, &hwpm_global_disable);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm global disable read failed");
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return err;
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}
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tegra_hwpm_dbg(hwpm, hwpm_info, "PROD_MODE fuse = 0x%x "
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"SECURITY_MODE fuse = 0x%x FA mode fuse = 0x%x"
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"HWPM_GLOBAL_DISABLE = 0x%x",
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production_mode, security_mode, fa_mode, hwpm_global_disable);
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/* Do not enable override if FA mode fuse is set */
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if (fa_mode != 0U) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"fa mode fuse enabled, no override required");
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return 0;
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}
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/* Override enable depends on security mode and global hwpm disable */
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if ((security_mode == 0U) &&
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(hwpm_global_disable == TEGRA_HWPM_GLOBAL_DISABLE_DISABLED)) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"security fuses are disabled, no override required");
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return 0;
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}
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for (idx = 0U; idx < active_chip->get_ip_max_idx(hwpm); idx++) {
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chip_ip = active_chip->chip_ips[idx];
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if ((hwpm_global_disable !=
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TEGRA_HWPM_GLOBAL_DISABLE_DISABLED) &&
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((chip_ip->dependent_fuse_mask &
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TEGRA_HWPM_FUSE_HWPM_GLOBAL_DISABLE_MASK) != 0U)) {
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/* HWPM disable is true */
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/* IP depends on HWPM global disable */
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chip_ip->override_enable = true;
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} else {
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/* HWPM disable is false */
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if ((security_mode != 0U) &&
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((chip_ip->dependent_fuse_mask &
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TEGRA_HWPM_FUSE_SECURITY_MODE_MASK) != 0U)) {
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/* Security mode fuse is set */
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/* IP depends on security mode fuse */
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chip_ip->override_enable = true;
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} else {
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/*
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* This is a valid case since not all IPs
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* depend on security fuse.
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*/
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"IP %d not overridden", idx);
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}
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}
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}
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return 0;
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}
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int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm)
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{
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int ret = 0;
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tegra_hwpm_fn(hwpm, " ");
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#if defined(CONFIG_HWPM_ALLOW_FORCE_ENABLE)
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#if defined(CONFIG_T234_HWPM_IP_MSS_CHANNEL)
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/* MSS CHANNEL */
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if (is_tegra_hypervisor_mode()) {
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mc0_base_r(),
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T234_HWPM_IP_MSS_CHANNEL, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_MSS_CHANNEL force enable failed");
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return ret;
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}
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}
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#endif
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#if defined(CONFIG_T234_HWPM_IP_MSS_GPU_HUB)
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/* MSS GPU HUB */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mss_nvlink_1_base_r(),
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T234_HWPM_IP_MSS_GPU_HUB, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_MSS_GPU_HUB force enable failed");
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return ret;
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}
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#endif
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if (tegra_platform_is_silicon()) {
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/* Static IP instances corresponding to silicon */
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/* VI */
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/*
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#if defined(CONFIG_T234_HWPM_IP_VI)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_vi_thi_base_r(),
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T234_HWPM_IP_VI, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_VI force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_vi2_thi_base_r(),
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T234_HWPM_IP_VI, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_VI force enable failed");
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return ret;
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}
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#endif
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*/
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#if defined(CONFIG_T234_HWPM_IP_ISP)
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/* ISP */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_isp_thi_base_r(),
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T234_HWPM_IP_ISP, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_ISP force enable failed");
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return ret;
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}
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#endif
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/* MGBE */
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/*
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#if defined(CONFIG_T234_HWPM_IP_MGBE)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_mgbe0_mac_rm_base_r(),
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T234_HWPM_IP_MGBE, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_MGBE force enable failed");
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return ret;
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}
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#endif
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*/
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#if defined(CONFIG_T234_HWPM_IP_NVDEC)
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/* NVDEC */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_nvdec_base_r(),
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T234_HWPM_IP_NVDEC, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_NVDEC force enable failed");
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return ret;
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}
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#endif
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/* PCIE */
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/*
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#if defined(CONFIG_T234_HWPM_IP_PCIE)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_pcie_c1_ctl_base_r(),
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T234_HWPM_IP_PCIE, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_PCIE force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_pcie_c4_ctl_base_r(),
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T234_HWPM_IP_PCIE, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_PCIE force enable failed");
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return ret;
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}
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_pcie_c5_ctl_base_r(),
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T234_HWPM_IP_PCIE, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_PCIE force enable failed");
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return ret;
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}
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#endif
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*/
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/* DISPLAY */
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/*
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#if defined(CONFIG_T234_HWPM_IP_DISPLAY)
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_disp_base_r(),
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T234_HWPM_IP_DISPLAY, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_DISPLAY force enable failed");
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return ret;
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}
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#endif
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*/
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}
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#endif
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/*
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* SCF is an independent IP with a single perfmon only.
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* SCF should not be part of force enable config flag.
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*/
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#if defined(CONFIG_T234_HWPM_IP_SCF)
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/* SCF */
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ret = tegra_hwpm_set_fs_info_ip_ops(hwpm, NULL,
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addr_map_rpg_pm_scf_base_r(),
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T234_HWPM_IP_SCF, true);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"T234_HWPM_IP_SCF force enable failed");
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return ret;
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}
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#endif
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return ret;
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}
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int t234_hwpm_get_fs_info(struct tegra_soc_hwpm *hwpm,
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u32 ip_enum, u64 *fs_mask, u8 *ip_status)
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{
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u32 ip_idx = 0U, inst_idx = 0U, element_mask_shift = 0U;
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u64 floorsweep = 0ULL;
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struct tegra_soc_hwpm_chip *active_chip = NULL;
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struct hwpm_ip *chip_ip = NULL;
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struct hwpm_ip_inst *ip_inst = NULL;
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|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
/* Convert tegra_soc_hwpm_ip enum to internal ip index */
|
|
if (hwpm->active_chip->is_ip_active(hwpm, ip_enum, &ip_idx)) {
|
|
active_chip = hwpm->active_chip;
|
|
chip_ip = active_chip->chip_ips[ip_idx];
|
|
if (!(chip_ip->override_enable) && chip_ip->inst_fs_mask) {
|
|
for (inst_idx = 0U; inst_idx < chip_ip->num_instances;
|
|
inst_idx++) {
|
|
ip_inst = &chip_ip->ip_inst_static_array[
|
|
inst_idx];
|
|
element_mask_shift = (inst_idx == 0U ? 0U :
|
|
ip_inst->num_core_elements_per_inst);
|
|
|
|
if (ip_inst->hw_inst_mask &
|
|
chip_ip->inst_fs_mask) {
|
|
floorsweep |= ((u64)
|
|
ip_inst->element_fs_mask <<
|
|
element_mask_shift);
|
|
}
|
|
}
|
|
*fs_mask = floorsweep;
|
|
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_VALID;
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_dbg_floorsweep_info,
|
|
"SOC hwpm IP %d is unavailable", ip_enum);
|
|
|
|
*ip_status = TEGRA_SOC_HWPM_IP_STATUS_INVALID;
|
|
*fs_mask = 0ULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int t234_hwpm_get_resource_info(struct tegra_soc_hwpm *hwpm,
|
|
u32 resource_enum, u8 *status)
|
|
{
|
|
u32 ip_idx = 0U;
|
|
struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
|
|
struct hwpm_ip *chip_ip = NULL;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
/* Convert tegra_soc_hwpm_resource to internal enum */
|
|
if (hwpm->active_chip->is_resource_active(hwpm, resource_enum, &ip_idx)) {
|
|
chip_ip = active_chip->chip_ips[ip_idx];
|
|
|
|
if (!(chip_ip->override_enable)) {
|
|
*status = tegra_hwpm_safe_cast_u32_to_u8(
|
|
chip_ip->resource_status);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
*status = tegra_hwpm_safe_cast_u32_to_u8(
|
|
TEGRA_HWPM_RESOURCE_STATUS_INVALID);
|
|
|
|
return 0;
|
|
}
|