mirror of
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4fbceccafa
A timeout of 100ms is provided to allow DG Map register values to propagate to router during Perfmon enable/disable functionality. This is a lot as ideally HW takes few us for the propagation. Hence, reduce the timeout value to 10ms. Bug 5072985 Signed-off-by: vasukis <vasukis@nvidia.com> Change-Id: Ie67a3325341824a451315d94afff3b5a1c0bb144 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3311261 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Yifei Wan <ywan@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Besar Wicaksono <bwicaksono@nvidia.com>
215 lines
7.6 KiB
C
215 lines
7.6 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm_static_analysis.h>
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#include <tegra_hwpm_timers.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t264/t264_internal.h>
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#include <hal/t264/hw/t264_pmasys_soc_hwpm.h>
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#include <hal/t264/hw/t264_pmmsys_soc_hwpm.h>
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#define TEGRA_HWPM_CBLOCK_CHANNEL_TO_CMD_SLICE(cblock, channel) \
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(((cblock) * pmmsys_num_channels_per_cblock_v()) + (channel))
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#define TEGRA_HWPM_MAX_SUPPORTED_DGS 256U
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#define TEGRA_HWPM_NUM_DG_STATUS_PER_REG \
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(TEGRA_HWPM_MAX_SUPPORTED_DGS / \
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pmmsys_router_user_dgmap_status_secure__size_1_v())
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int t264_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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u32 reg_val;
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u32 cblock = 0U;
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u32 channel = 0U;
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u32 dg_idx = 0U;
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u32 config_dgmap = 0U;
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u32 dgmap_status_reg_idx = 0U, dgmap_status_reg_dgidx = 0U;
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u32 retries = 10U;
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u32 sleep_msecs = 10U;
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int err = 0;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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NULL);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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/* Enable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_bind,
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"Enabling PERFMON(0x%llx - 0x%llx)",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa);
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/*
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* HWPM readl function expects register address relative to
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* perfmon group base address.
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* Hence use enginestatus offset + perfmon base_pa as the register
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*/
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tegra_hwpm_readl(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_enginestatus_o(),
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perfmon->base_pa), ®_val);
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reg_val = set_field(reg_val, pmmsys_enginestatus_enable_m(),
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pmmsys_enginestatus_enable_out_f());
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tegra_hwpm_writel(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_enginestatus_o(),
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perfmon->base_pa), reg_val);
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/*
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* HWPM readl function expects register address relative to
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* perfmon group base address.
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* Hence use secure_config offset + perfmon base_pa as the register
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* The register also contains dg_idx programmed by HW that will be used
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* to poll dg mapping in router.
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*/
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tegra_hwpm_readl(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_secure_config_o(),
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perfmon->base_pa), &config_dgmap);
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dg_idx = pmmsys_secure_config_dg_idx_v(config_dgmap);
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/* Configure DG map for this perfmon */
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config_dgmap = set_field(config_dgmap,
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pmmsys_secure_config_cmd_slice_id_m() |
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pmmsys_secure_config_channel_id_m() |
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pmmsys_secure_config_cblock_id_m() |
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pmmsys_secure_config_mapped_m() |
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pmmsys_secure_config_use_prog_dg_idx_m() |
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pmmsys_secure_config_command_pkt_decoder_m(),
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pmmsys_secure_config_cmd_slice_id_f(
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TEGRA_HWPM_CBLOCK_CHANNEL_TO_CMD_SLICE(
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cblock, channel)) |
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pmmsys_secure_config_channel_id_f(channel) |
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pmmsys_secure_config_cblock_id_f(cblock) |
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pmmsys_secure_config_mapped_true_f() |
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pmmsys_secure_config_use_prog_dg_idx_false_f() |
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pmmsys_secure_config_command_pkt_decoder_enable_f());
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tegra_hwpm_writel(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_secure_config_o(),
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perfmon->base_pa), config_dgmap);
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/* Make sure that the DG map status is propagated to the router */
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dgmap_status_reg_idx = dg_idx / TEGRA_HWPM_NUM_DG_STATUS_PER_REG;
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dgmap_status_reg_dgidx = dg_idx % TEGRA_HWPM_NUM_DG_STATUS_PER_REG;
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tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux,
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pmmsys_router_user_dgmap_status_secure_r(dgmap_status_reg_idx),
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®_val,
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(((reg_val >> dgmap_status_reg_dgidx) &
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pmmsys_router_user_dgmap_status_secure_dg_s()) !=
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pmmsys_router_user_dgmap_status_secure_dg_mapped_v()),
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"Perfmon(0x%llx - 0x%llx) dgmap %d status update timed out",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa, dg_idx);
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return 0;
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}
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int t264_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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u32 reg_val;
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u32 dg_idx = 0U;
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u32 config_dgmap = 0U;
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u32 dgmap_status_reg_idx = 0U, dgmap_status_reg_dgidx = 0U;
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u32 retries = 10U;
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u32 sleep_msecs = 10U;
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int err = 0;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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if (perfmon->element_type == HWPM_ELEMENT_PERFMUX) {
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/*
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* Since HWPM elements use perfmon functions,
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* skip disabling HWPM PERFMUX elements
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*/
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return 0;
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}
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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NULL);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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/* Disable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_release_resource,
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"Disabling PERFMON(0x%llx - 0x%llx)",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa);
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/*
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* HWPM readl function expects register address relative to
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* perfmon group base address.
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* Hence use sys0_control offset + perfmon base_pa as the register
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*/
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tegra_hwpm_readl(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_control_o(),
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perfmon->base_pa), ®_val);
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reg_val = set_field(reg_val, pmmsys_control_mode_m(),
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pmmsys_control_mode_disable_f());
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tegra_hwpm_writel(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_control_o(),
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perfmon->base_pa), reg_val);
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/*
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* HWPM readl function expects register address relative to
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* perfmon group base address.
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* Hence use secure_config offset + perfmon base_pa as the register
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* The register also contains dg_idx programmed by HW that will be used
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* to poll dg mapping in router.
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*/
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tegra_hwpm_readl(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_secure_config_o(),
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perfmon->base_pa), &config_dgmap);
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dg_idx = pmmsys_secure_config_dg_idx_v(config_dgmap);
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/* Reset DG map for this perfmon */
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config_dgmap = set_field(config_dgmap,
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pmmsys_secure_config_mapped_m(),
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pmmsys_secure_config_mapped_false_f());
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tegra_hwpm_writel(hwpm, perfmon,
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tegra_hwpm_safe_add_u64(pmmsys_secure_config_o(),
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perfmon->base_pa), config_dgmap);
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/* Make sure that the DG map status is propagated to the router */
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dgmap_status_reg_idx = dg_idx / TEGRA_HWPM_NUM_DG_STATUS_PER_REG;
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dgmap_status_reg_dgidx = dg_idx % TEGRA_HWPM_NUM_DG_STATUS_PER_REG;
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tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux,
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pmmsys_router_user_dgmap_status_secure_r(dgmap_status_reg_idx),
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®_val,
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(((reg_val >> dgmap_status_reg_dgidx) &
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pmmsys_router_user_dgmap_status_secure_dg_s()) !=
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pmmsys_router_user_dgmap_status_secure_dg_not_mapped_v()),
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"Perfmon(0x%llx - 0x%llx) dgmap %d status update timed out",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa, dg_idx);
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return 0;
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}
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