mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-23 18:01:07 +03:00
7dd5b5c956
PMA and RTR perfmuxes contain registers required to configure HWPM. So currently, PMA and RTR IPs are treated as special case and initialized - released along with the driver. However, as RTR IP includes both router and pma apertures, only treat RTR as special IP. Change RTR config to have router and pma apertures as separate instances. Define macros for router and pma instance index. This will be allow to retrieve router and pma aperture structures. Remove PMA IP reservation during driver init and PMA IP release at driver close. As PMA IP is not treated special now, remove get_pma_ip_idx() HAL. Modify HWPM configuration functions to use router and pma apertures initialized as part of RTR IP. Jira THWPM-41 Change-Id: Ic82b2d07769c1b5c4601e07776be06087468657d Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2706488 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <soc/tegra/fuse.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_static_analysis.h>
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int tegra_hwpm_func_single_aperture(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip,
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u32 inst_idx, u32 aperture_idx, enum hwpm_aperture_type a_type)
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{
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struct hwpm_ip_aperture *aperture = NULL;
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int err = 0, ret = 0;
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if (a_type == HWPM_APERTURE_PERFMUX) {
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aperture = chip_ip->ip_perfmux[aperture_idx];
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} else if (a_type == HWPM_APERTURE_PERFMON) {
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aperture = chip_ip->ip_perfmon[aperture_idx];
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} else {
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tegra_hwpm_err(hwpm, "INVALID a_type %d", a_type);
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return -EINVAL;
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}
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if (aperture == NULL) {
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return 0;
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}
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if (aperture->hw_inst_mask != BIT(inst_idx)) {
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return 0;
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}
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switch (iia_func) {
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case TEGRA_HWPM_GET_ALIST_SIZE:
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if (aperture->alist) {
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hwpm->full_alist_size =
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tegra_hwpm_safe_add_u64(
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hwpm->full_alist_size,
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aperture->alist_size);
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} else {
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tegra_hwpm_err(hwpm, "IP %d"
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" aperture type %d idx %d NULL alist",
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ip_idx, a_type, aperture_idx);
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}
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break;
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case TEGRA_HWPM_COMBINE_ALIST:
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err = hwpm->active_chip->copy_alist(hwpm,
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aperture, func_args->alist, &func_args->full_alist_idx);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d"
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" aperture type %d idx %d alist copy failed",
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ip_idx, a_type, aperture_idx);
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return err;
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}
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break;
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case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE:
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if (a_type == HWPM_APERTURE_PERFMUX) {
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err = tegra_hwpm_perfmux_reserve(hwpm, aperture);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d reserve failed",
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ip_idx, aperture_idx);
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goto fail;
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}
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} else if (a_type == HWPM_APERTURE_PERFMON) {
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err = tegra_hwpm_perfmon_reserve(hwpm, aperture);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d reserve failed",
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ip_idx, aperture_idx);
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goto fail;
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}
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}
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break;
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case TEGRA_HWPM_RELEASE_RESOURCES:
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if (a_type == HWPM_APERTURE_PERFMUX) {
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ret = hwpm->active_chip->perfmux_disable(hwpm, aperture);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d disable failed",
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ip_idx, aperture_idx);
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}
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ret = tegra_hwpm_perfmux_release(hwpm, aperture);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d release failed",
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ip_idx, aperture_idx);
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}
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} else if (a_type == HWPM_APERTURE_PERFMON) {
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ret = hwpm->active_chip->perfmon_disable(hwpm, aperture);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d disable failed",
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ip_idx, aperture_idx);
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}
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ret = tegra_hwpm_perfmon_release(hwpm, aperture);
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if (ret != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d release failed",
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ip_idx, aperture_idx);
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}
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}
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break;
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case TEGRA_HWPM_BIND_RESOURCES:
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err = hwpm->active_chip->zero_alist_regs(hwpm, aperture);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d zero regs failed",
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ip_idx, aperture_idx);
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goto fail;
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}
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if (a_type == HWPM_APERTURE_PERFMON) {
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err = hwpm->active_chip->perfmon_enable(hwpm, aperture);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "IP %d aperture"
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" type %d idx %d enable failed",
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ip_idx, aperture_idx);
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goto fail;
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}
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}
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break;
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default:
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tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func);
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return -EINVAL;
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break;
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}
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return 0;
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fail:
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return err;
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}
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int tegra_hwpm_func_all_perfmons(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip,
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u32 inst_idx)
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{
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u32 perfmon_idx;
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int err = 0;
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for (perfmon_idx = 0U; perfmon_idx < chip_ip->num_perfmon_slots;
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perfmon_idx++) {
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err = tegra_hwpm_func_single_aperture(
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hwpm, func_args, iia_func, ip_idx,
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chip_ip, inst_idx, perfmon_idx, HWPM_APERTURE_PERFMON);
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if (err < 0) {
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tegra_hwpm_err(hwpm,
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"IP %d inst %d perfmon %d func 0x%x failed",
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ip_idx, inst_idx, perfmon_idx, iia_func);
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goto fail;
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}
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}
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return 0;
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fail:
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return err;
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}
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int tegra_hwpm_func_all_perfmuxes(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip,
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u32 inst_idx)
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{
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u32 perfmux_idx;
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int err = 0;
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for (perfmux_idx = 0U; perfmux_idx < chip_ip->num_perfmux_slots;
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perfmux_idx++) {
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err = tegra_hwpm_func_single_aperture(
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hwpm, func_args, iia_func, ip_idx,
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chip_ip, inst_idx, perfmux_idx, HWPM_APERTURE_PERFMUX);
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if (err < 0) {
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tegra_hwpm_err(hwpm,
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"IP %d inst %d perfmux %d func 0x%x failed",
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ip_idx, inst_idx, perfmux_idx, iia_func);
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goto fail;
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}
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}
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return 0;
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fail:
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return err;
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}
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int tegra_hwpm_func_all_inst(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func, u32 ip_idx, struct hwpm_ip *chip_ip)
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{
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unsigned long inst_idx = 0UL;
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unsigned long floorsweep_info = 0UL;
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unsigned long reserved_insts = 0UL;
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int err = 0;
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/* Execute tasks for all instances if any */
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floorsweep_info = (unsigned long)chip_ip->fs_mask;
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for_each_set_bit(inst_idx, &floorsweep_info, 32U) {
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switch (iia_func) {
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case TEGRA_HWPM_GET_ALIST_SIZE:
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/* do nothing, continue to apertures */
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break;
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case TEGRA_HWPM_COMBINE_ALIST:
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func_args->full_alist_idx = 0ULL;
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break;
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case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE:
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/* do nothing, continue to apertures */
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break;
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case TEGRA_HWPM_BIND_RESOURCES:
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/* do nothing, continue to instances */
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break;
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case TEGRA_HWPM_RELEASE_RESOURCES:
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/* do nothing, continue to instances */
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break;
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default:
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tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func);
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goto fail;
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break;
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}
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/* Continue functionality for all apertures */
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err = tegra_hwpm_func_all_perfmuxes(
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hwpm, func_args, iia_func, ip_idx, chip_ip, inst_idx);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed",
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ip_idx, inst_idx, iia_func);
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goto fail;
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}
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err = tegra_hwpm_func_all_perfmons(
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hwpm, func_args, iia_func, ip_idx, chip_ip, inst_idx);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "IP %d inst %d func 0x%x failed",
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ip_idx, inst_idx, iia_func);
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goto fail;
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}
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/* Post execute functionality */
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switch (iia_func) {
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case TEGRA_HWPM_GET_ALIST_SIZE:
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/* do nothing, continue to apertures */
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break;
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case TEGRA_HWPM_COMBINE_ALIST:
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/* do nothing, continue to apertures */
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break;
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case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE:
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reserved_insts |= BIT(inst_idx);
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break;
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case TEGRA_HWPM_BIND_RESOURCES:
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/* do nothing, continue to instances */
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break;
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case TEGRA_HWPM_RELEASE_RESOURCES:
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/* do nothing, continue to instances */
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break;
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default:
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tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func);
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goto fail;
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break;
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}
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}
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return 0;
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fail:
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if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) {
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/* Revert previously reserved instances of this IP */
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for_each_set_bit(inst_idx, &reserved_insts, 32U) {
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/* Release all apertures belonging to this instance */
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err = tegra_hwpm_func_all_perfmuxes(hwpm, func_args,
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TEGRA_HWPM_RELEASE_RESOURCES, ip_idx,
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chip_ip, inst_idx);
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if (err < 0) {
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tegra_hwpm_err(hwpm,
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"IP %d inst %d func 0x%x failed",
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ip_idx, inst_idx, iia_func);
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return err;
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}
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err = tegra_hwpm_func_all_perfmons(hwpm, func_args,
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TEGRA_HWPM_RELEASE_RESOURCES, ip_idx,
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chip_ip, inst_idx);
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if (err < 0) {
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tegra_hwpm_err(hwpm,
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"IP %d inst %d func 0x%x failed",
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ip_idx, inst_idx, iia_func);
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return err;
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}
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}
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}
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return err;
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}
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int tegra_hwpm_func_single_ip(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func, u32 ip_idx)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[ip_idx];
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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if (chip_ip == NULL) {
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tegra_hwpm_err(hwpm, "IP %d not populated", ip_idx);
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return -ENODEV;
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}
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switch (iia_func) {
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case TEGRA_HWPM_GET_ALIST_SIZE:
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case TEGRA_HWPM_COMBINE_ALIST:
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case TEGRA_HWPM_BIND_RESOURCES:
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/* Skip unavailable IPs */
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if (!chip_ip->reserved) {
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return 0;
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}
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if (chip_ip->fs_mask == 0U) {
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/* No IP instance is available */
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return 0;
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}
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break;
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case TEGRA_HWPM_RESERVE_GIVEN_RESOURCE:
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/* PMA and RTR are already reserved */
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if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) {
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return 0;
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}
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/* Skip IPs which are already reserved */
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if (chip_ip->reserved) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Chip IP %d already reserved", ip_idx);
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return 0;
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}
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/* Make sure IP override is not enabled */
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if (chip_ip->override_enable) {
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Chip IP %d not available", ip_idx);
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return 0;
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}
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break;
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case TEGRA_HWPM_RELEASE_RESOURCES:
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/* PMA and RTR will be released later */
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if (ip_idx == active_chip->get_rtr_int_idx(hwpm)) {
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return 0;
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}
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/* Skip unavailable IPs */
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if (!chip_ip->reserved) {
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return 0;
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}
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if (chip_ip->fs_mask == 0U) {
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/* No IP instance is available */
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return 0;
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}
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break;
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default:
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tegra_hwpm_err(hwpm, "func 0x%x unknown", iia_func);
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goto fail;
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break;
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}
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/* Continue functionality for all instances in this IP */
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err = tegra_hwpm_func_all_inst(hwpm, func_args, iia_func,
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ip_idx, chip_ip);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "IP %d func 0x%x failed",
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ip_idx, iia_func);
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goto fail;
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}
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/* Post execute functionality */
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if (iia_func == TEGRA_HWPM_RESERVE_GIVEN_RESOURCE) {
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chip_ip->reserved = true;
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}
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if (iia_func == TEGRA_HWPM_RELEASE_RESOURCES) {
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chip_ip->reserved = false;
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}
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return 0;
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fail:
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return err;
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}
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int tegra_hwpm_func_all_ip(struct tegra_soc_hwpm *hwpm,
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struct tegra_hwpm_func_args *func_args,
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enum tegra_hwpm_funcs iia_func)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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u32 ip_idx;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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for (ip_idx = 0U; ip_idx < active_chip->get_ip_max_idx(hwpm);
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ip_idx++) {
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err = tegra_hwpm_func_single_ip(
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hwpm, func_args, iia_func, ip_idx);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "IP %d func 0x%x failed",
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ip_idx, iia_func);
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goto fail;
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}
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}
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return 0;
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fail:
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return err;
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}
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int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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u32 ip_idx = TEGRA_SOC_HWPM_IP_INACTIVE;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"User requesting to reserve resource %d", resource);
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/* Translate resource to ip_idx */
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if (!active_chip->is_resource_active(hwpm, resource, &ip_idx)) {
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tegra_hwpm_err(hwpm, "Requested resource %d is unavailable",
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resource);
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/* Remove after uapi update */
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if (resource == TEGRA_SOC_HWPM_RESOURCE_MSS_NVLINK) {
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tegra_hwpm_dbg(hwpm, hwpm_verbose,
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"ignoring resource %d", resource);
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return 0;
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}
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return -EINVAL;
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}
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err = tegra_hwpm_func_single_ip(hwpm, NULL,
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TEGRA_HWPM_RESERVE_GIVEN_RESOURCE, ip_idx);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "failed to reserve IP %d", ip_idx);
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return err;
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}
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return 0;
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}
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int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
err = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_BIND_RESOURCES);
|
|
if (err != 0) {
|
|
tegra_hwpm_err(hwpm, "failed to bind resources");
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm)
|
|
{
|
|
int ret = 0;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
ret = tegra_hwpm_func_all_ip(hwpm, NULL, TEGRA_HWPM_RELEASE_RESOURCES);
|
|
if (ret != 0) {
|
|
tegra_hwpm_err(hwpm, "failed to release resources");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|