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efd031dcb0
Add mode E user data test for these IPS: - NVTHERM - IPMU JIRA MSST-831 Change-Id: Id8911fa9bbed47f1c5d1e82b075e60134e05ad2c Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3361434 Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Yifei Wan <ywan@nvidia.com>
120 lines
3.4 KiB
C++
120 lines
3.4 KiB
C++
/* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: GPL-2.0-only
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef T410_TEST_H
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#define T410_TEST_H
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#include "nv_soc_hwpm_test.h"
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#include <vector>
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#include <cstdint>
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#define T410_MAX_SOCKETS 2
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class T410Tests : public NvSocHwpmTests
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{
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public:
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T410Tests();
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~T410Tests() override;
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protected:
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struct PmaConfigurationParams {
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PmaConfigurationParams()
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{
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enable_streaming = false;
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pulse_interval = 0;
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enable_pma_record = false;
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keep_latest = false;
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}
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bool enable_streaming;
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uint32_t pulse_interval;
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bool enable_pma_record;
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bool keep_latest;
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};
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struct PmmConfigurationParams {
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enum Mode {
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MODE_B,
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MODE_C,
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MODE_E,
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MODE_E_USERDATA
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};
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PmmConfigurationParams()
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{
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mode = MODE_B;
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perfmon_idx = 0;
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perfmon_base = 0;
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enable_local_triggering = false;
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enable_overflow_priming = false;
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collect_one = false;
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}
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std::vector<uint32_t> expected_sig_val;
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Mode mode;
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uint32_t perfmon_idx;
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uint64_t perfmon_base;
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bool enable_local_triggering;
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bool enable_overflow_priming;
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bool collect_one;
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};
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void SetUp(void) override;
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void TearDown(void) override;
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void GetDevices(void);
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void TestRegopsRead(nv_soc_hwpm_session session,
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uint64_t pma_record_buffer_pma_va,
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size_t record_buffer_size);
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void TestRegopsWrite(nv_soc_hwpm_session session);
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void RegOpWrite32(
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nv_soc_hwpm_session session, uint64_t address, uint32_t value, uint32_t mask);
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void RegOpRead32(
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nv_soc_hwpm_session session, uint64_t address, uint32_t *value);
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void SetupPma(nv_soc_hwpm_session session, const PmaConfigurationParams ¶ms);
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void EnablePmaStreaming(nv_soc_hwpm_session session, const PmaConfigurationParams ¶ms);
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void SetupPmm(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void SetupWatchbusPma(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void SetupWatchbusNvtherm(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void SetupWatchbusCsnMbn(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void SetupWatchbusIpmu(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void TeardownPma(nv_soc_hwpm_session session);
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void TeardownPmm(nv_soc_hwpm_session session, const PmmConfigurationParams ¶ms);
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void TeardownPerfmux(nv_soc_hwpm_session session);
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void IssuePmaTrigger(
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nv_soc_hwpm_session session,
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bool halt_before_trigger = false,
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bool halt_after_trigger = false,
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uint32_t delay_after_trigger = 0);
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void HarvestCounters(
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nv_soc_hwpm_session session,
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const PmmConfigurationParams ¶ms,
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const uint32_t sig_val[4]);
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void InitPmmParams(nv_soc_hwpm_resource resource, PmmConfigurationParams ¶ms);
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void ModeBTest(nv_soc_hwpm_resource resource);
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void ModeETest(nv_soc_hwpm_resource resource);
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void ModeETestUserData(nv_soc_hwpm_resource resource);
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nv_soc_hwpm_device t410_dev[T410_MAX_SOCKETS];
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uint32_t t410_dev_count;
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};
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#endif // T410_TEST_H
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