mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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Move chip specific code to chip specific folder. This will allow multiple chip support in the future. Create new specific functions - Initialize hwpm structures - Reserve and release PMA and RTR apertures - Zero, update and check allowlists - Set and get fake registers for MC aperture on simulation - perfmon dt aperture enums Jira THWPM-41 Change-Id: Ib80f324283c8d29b5c6f7bb6345a6df2410954e6 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2620234 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
172 lines
4.6 KiB
C
172 lines
4.6 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <tegra-soc-hwpm.h>
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#include <hal/tegra_soc_hwpm_init.h>
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#include <hal/t234/t234_soc_hwpm_init.h>
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void __iomem **tegra_soc_hwpm_init_dt_apertures(void)
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{
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return t234_soc_hwpm_init_dt_apertures();
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}
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struct tegra_soc_hwpm_ip_ops *tegra_soc_hwpm_init_ip_ops_info(void)
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{
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return t234_soc_hwpm_init_ip_ops_info();
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}
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bool tegra_soc_hwpm_is_perfmon(u32 dt_aperture)
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{
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return t234_soc_hwpm_is_perfmon(dt_aperture);
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}
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u64 tegra_soc_hwpm_get_perfmon_base(u32 dt_aperture)
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{
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return t234_soc_hwpm_get_perfmon_base(dt_aperture);
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}
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bool tegra_soc_hwpm_is_dt_aperture(u32 dt_aperture)
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{
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return t234_soc_hwpm_is_dt_aperture(dt_aperture);
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}
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bool tegra_soc_hwpm_is_dt_aperture_reserved(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture, u32 rsrc_id)
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{
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return t234_soc_hwpm_is_dt_aperture_reserved(hwpm, aperture, rsrc_id);
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}
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u32 tegra_soc_hwpm_get_ip_aperture(struct tegra_soc_hwpm *hwpm,
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u64 phys_address, u64 *ip_base_addr)
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{
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return t234_soc_hwpm_get_ip_aperture(hwpm, phys_address, ip_base_addr);
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}
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struct hwpm_resource_aperture *tegra_soc_hwpm_find_aperture(
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struct tegra_soc_hwpm *hwpm, u64 phys_addr,
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bool use_absolute_base, bool check_reservation,
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u64 *updated_pa)
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{
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return t234_soc_hwpm_find_aperture(hwpm, phys_addr,
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use_absolute_base, check_reservation, updated_pa);
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}
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int tegra_soc_hwpm_fs_info_init(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_fs_info_init(hwpm);
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}
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int tegra_soc_hwpm_disable_pma_triggers(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_disable_pma_triggers(hwpm);
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}
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u32 **tegra_soc_hwpm_get_mc_fake_regs(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture)
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{
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return t234_soc_hwpm_get_mc_fake_regs(hwpm, aperture);
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}
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void tegra_soc_hwpm_set_mc_fake_regs(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture,
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bool set_null)
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{
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t234_soc_hwpm_set_mc_fake_regs(hwpm, aperture, set_null);
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}
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int tegra_soc_hwpm_disable_slcg(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_disable_slcg(hwpm);
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}
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int tegra_soc_hwpm_enable_slcg(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_enable_slcg(hwpm);
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}
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void tegra_soc_hwpm_zero_alist_regs(struct tegra_soc_hwpm *hwpm,
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struct hwpm_resource_aperture *aperture)
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{
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t234_soc_hwpm_zero_alist_regs(hwpm, aperture);
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}
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int tegra_soc_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct)
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{
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return t234_soc_hwpm_update_allowlist(hwpm, ioctl_struct);
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}
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bool tegra_soc_hwpm_allowlist_check(struct hwpm_resource_aperture *aperture,
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u64 phys_addr, bool use_absolute_base,
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u64 *updated_pa)
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{
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return t234_soc_hwpm_allowlist_check(aperture, phys_addr,
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use_absolute_base, updated_pa);
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}
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void tegra_soc_hwpm_get_full_allowlist(struct tegra_soc_hwpm *hwpm)
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{
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t234_soc_hwpm_get_full_allowlist(hwpm);
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}
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int tegra_soc_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_update_get_put *update_get_put)
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{
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return t234_soc_hwpm_update_mem_bytes(hwpm, update_get_put);
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}
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int tegra_soc_hwpm_clear_pipeline(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_clear_pipeline(hwpm);
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}
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int tegra_soc_hwpm_stream_buf_map(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream)
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{
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return t234_soc_hwpm_stream_buf_map(hwpm, alloc_pma_stream);
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}
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int tegra_soc_hwpm_pma_rtr_map(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_pma_rtr_map(hwpm);
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}
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int tegra_soc_hwpm_pma_rtr_unmap(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_pma_rtr_unmap(hwpm);
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}
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int tegra_soc_hwpm_reserve_given_resource(struct tegra_soc_hwpm *hwpm, u32 resource)
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{
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return t234_soc_hwpm_reserve_given_resource(hwpm, resource);
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}
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void tegra_soc_hwpm_reset_resources(struct tegra_soc_hwpm *hwpm)
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{
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t234_soc_hwpm_reset_resources(hwpm);
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}
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void tegra_soc_hwpm_disable_perfmons(struct tegra_soc_hwpm *hwpm)
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{
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t234_soc_hwpm_disable_perfmons(hwpm);
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}
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int tegra_soc_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm)
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{
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return t234_soc_hwpm_bind_resources(hwpm);
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}
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