mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-25 02:34:23 +03:00
92be6f7a00
- Update HWPM driver to add HAL layer. This will allow support for multiple chips. - Add below data structure hierarchy for HWPM driver HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon" - Chip info structure contains - Array of IP info - HAL function pointers - IP info structure contains IP specific info - Number of instances - Number of apertures per instance - Aperture ranges, strides, static info array - Aperture dynamic arrays - Aperture info structure contains - Hw index - Physical address info - MMIO address info - Add separate IP info files - Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible. - Move probe, ioctl and io functions to os/linux path. - Add fn, info, register and verbose debug log levels to controls debug messages - add debugfs node to update dbg_mask - Correct MGBE perfmux base address Jira THWPM-41 Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
79 lines
2.2 KiB
C
79 lines
2.2 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <soc/tegra/fuse.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_common.h>
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int tegra_soc_hwpm_exec_regops(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_exec_reg_ops *exec_reg_ops)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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int op_idx = 0;
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struct tegra_soc_hwpm_reg_op *reg_op = NULL;
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int ret = 0;
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tegra_hwpm_fn(hwpm, " ");
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switch (exec_reg_ops->mode) {
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case TEGRA_SOC_HWPM_REG_OP_MODE_FAIL_ON_FIRST:
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case TEGRA_SOC_HWPM_REG_OP_MODE_CONT_ON_ERR:
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break;
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default:
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tegra_hwpm_err(hwpm, "Invalid reg ops mode(%u)",
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exec_reg_ops->mode);
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return -EINVAL;
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}
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if (exec_reg_ops->op_count > TEGRA_SOC_HWPM_REG_OPS_SIZE) {
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tegra_hwpm_err(hwpm, "Reg_op count=%d exceeds max count",
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exec_reg_ops->op_count);
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return -EINVAL;
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}
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if (active_chip->exec_reg_ops == NULL) {
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tegra_hwpm_err(hwpm, "exec_reg_ops uninitialized");
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return -ENODEV;
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}
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/*
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* Initialize flag to true assuming all regops will pass
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* If any regop fails, the flag will be reset to false.
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*/
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exec_reg_ops->b_all_reg_ops_passed = true;
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for (op_idx = 0; op_idx < exec_reg_ops->op_count; op_idx++) {
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reg_op = &(exec_reg_ops->ops[op_idx]);
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tegra_hwpm_dbg(hwpm, hwpm_verbose,
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"reg op: idx(%d), phys(0x%llx), cmd(%u)",
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op_idx, reg_op->phys_addr, reg_op->cmd);
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ret = active_chip->exec_reg_ops(hwpm, reg_op);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "exec_reg_ops %d failed", op_idx);
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exec_reg_ops->b_all_reg_ops_passed = false;
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if (exec_reg_ops->mode ==
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TEGRA_SOC_HWPM_REG_OP_MODE_FAIL_ON_FIRST) {
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return -EINVAL;
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}
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}
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}
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return 0;
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}
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