mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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92be6f7a00
- Update HWPM driver to add HAL layer. This will allow support for multiple chips. - Add below data structure hierarchy for HWPM driver HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon" - Chip info structure contains - Array of IP info - HAL function pointers - IP info structure contains IP specific info - Number of instances - Number of apertures per instance - Aperture ranges, strides, static info array - Aperture dynamic arrays - Aperture info structure contains - Hw index - Physical address info - MMIO address info - Add separate IP info files - Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible. - Move probe, ioctl and io functions to os/linux path. - Add fn, info, register and verbose debug log levels to controls debug messages - add debugfs node to update dbg_mask - Correct MGBE perfmux base address Jira THWPM-41 Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
66 lines
2.0 KiB
C
66 lines
2.0 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef TEGRA_HWPM_IO_H
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#define TEGRA_HWPM_IO_H
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/**
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* Sets a particular field value in input data.
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*
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* Uses mask to clear specific bit positions in curr_val. field_val
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* is used to set the bits in curr_val to be returned.
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* Note: Function does not perform any validation of input parameters.
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*
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* curr_val [in] Current input data value.
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*
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* mask [in] Mask of the bits to be updated.
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*
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* field_val [in] Value to change the mask bits to.
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*
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* Returns updated value.
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*/
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static inline u32 set_field(u32 curr_val, u32 mask, u32 field_val)
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{
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return ((curr_val & ~mask) | field_val);
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}
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/**
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* Retrieve value of specific bits from input data.
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* Note: Function does not perform any validation of input parameters.
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*
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* input_data [in] Data to retrieve value from.
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*
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* mask [in] Mask of the bits to get value from.
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*
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* Return value from input_data corresponding to mask bits.
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*/
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static inline u32 get_field(u32 input_data, u32 mask)
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{
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return (input_data & mask);
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}
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struct tegra_soc_hwpm;
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struct hwpm_ip_aperture;
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u32 tegra_hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr);
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void tegra_hwpm_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 val);
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u32 regops_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr);
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void regops_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 val);
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#endif /* TEGRA_HWPM_IO_H */
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