mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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0cb6f6b48f
- Generate HWPM hw headers using register generator tool. - Add required hw headers to include/hw/ path - Update driver code to replace static hw defines with hw header definitions. - Remove unused static hw defines. THWPM-39 Change-Id: I57566d51657bb6b22c4b581acd257f1871438adf Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2552741 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
166 lines
11 KiB
C
166 lines
11 KiB
C
/*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* Function/Macro naming determines intended use:
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*
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* <x>_r(void) : Returns the offset for register <x>.
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*
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* <x>_o(void) : Returns the offset for element <x>.
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*
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* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
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*
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* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
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*
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* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
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* and masked to place it at field <y> of register <x>. This value
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* can be |'d with others to produce a full register value for
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* register <x>.
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*
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* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
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* value can be ~'d and then &'d to clear the value of field <y> for
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* register <x>.
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*
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* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
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* to place it at field <y> of register <x>. This value can be |'d
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* with others to produce a full register value for <x>.
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*
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* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
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* <x> value 'r' after being shifted to place its LSB at bit 0.
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* This value is suitable for direct comparison with other unshifted
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* values appropriate for use in field <y> of register <x>.
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*
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* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
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* field <y> of register <x>. This value is suitable for direct
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* comparison with unshifted values appropriate for use in field <y>
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* of register <x>.
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*/
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#ifndef TEGRA_HW_ADDR_MAP_SOC_HWPM_H
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#define TEGRA_HW_ADDR_MAP_SOC_HWPM_H
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#define addr_map_rpg_pm_base_r() (0x0f100000U)
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#define addr_map_rpg_pm_limit_r() (0x0f149fffU)
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#define addr_map_pma_base_r() (0x0f14a000U)
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#define addr_map_rtr_base_r() (0x0f14d000U)
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#define addr_map_disp_base_r() (0x13800000U)
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#define addr_map_disp_limit_r() (0x138effffU)
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#define addr_map_vi_thi_base_r() (0x15f00000U)
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#define addr_map_vi_thi_limit_r() (0x15ffffffU)
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#define addr_map_vi2_thi_base_r() (0x14f00000U)
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#define addr_map_vi2_thi_limit_r() (0x14ffffffU)
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#define addr_map_vic_base_r() (0x15340000U)
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#define addr_map_vic_limit_r() (0x1537ffffU)
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#define addr_map_nvdec_base_r() (0x15480000U)
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#define addr_map_nvdec_limit_r() (0x154bffffU)
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#define addr_map_nvenc_base_r() (0x154c0000U)
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#define addr_map_nvenc_limit_r() (0x154fffffU)
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#define addr_map_ofa_base_r() (0x15a50000U)
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#define addr_map_ofa_limit_r() (0x15a5ffffU)
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#define addr_map_isp_thi_base_r() (0x14b00000U)
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#define addr_map_isp_thi_limit_r() (0x14bfffffU)
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#define addr_map_pcie_c0_ctl_base_r() (0x14180000U)
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#define addr_map_pcie_c0_ctl_limit_r() (0x1419ffffU)
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#define addr_map_pcie_c1_ctl_base_r() (0x14100000U)
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#define addr_map_pcie_c1_ctl_limit_r() (0x1411ffffU)
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#define addr_map_pcie_c2_ctl_base_r() (0x14120000U)
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#define addr_map_pcie_c2_ctl_limit_r() (0x1413ffffU)
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#define addr_map_pcie_c3_ctl_base_r() (0x14140000U)
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#define addr_map_pcie_c3_ctl_limit_r() (0x1415ffffU)
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#define addr_map_pcie_c4_ctl_base_r() (0x14160000U)
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#define addr_map_pcie_c4_ctl_limit_r() (0x1417ffffU)
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#define addr_map_pcie_c5_ctl_base_r() (0x141a0000U)
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#define addr_map_pcie_c5_ctl_limit_r() (0x141bffffU)
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#define addr_map_pcie_c6_ctl_base_r() (0x141c0000U)
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#define addr_map_pcie_c6_ctl_limit_r() (0x141dffffU)
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#define addr_map_pcie_c7_ctl_base_r() (0x141e0000U)
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#define addr_map_pcie_c7_ctl_limit_r() (0x141fffffU)
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#define addr_map_pcie_c8_ctl_base_r() (0x140a0000U)
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#define addr_map_pcie_c8_ctl_limit_r() (0x140bffffU)
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#define addr_map_pcie_c9_ctl_base_r() (0x140c0000U)
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#define addr_map_pcie_c9_ctl_limit_r() (0x140dffffU)
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#define addr_map_pcie_c10_ctl_base_r() (0x140e0000U)
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#define addr_map_pcie_c10_ctl_limit_r() (0x140fffffU)
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#define addr_map_pva0_pm_base_r() (0x16200000U)
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#define addr_map_pva0_pm_limit_r() (0x1620ffffU)
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#define addr_map_nvdla0_base_r() (0x15880000U)
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#define addr_map_nvdla0_limit_r() (0x158bffffU)
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#define addr_map_nvdla1_base_r() (0x158c0000U)
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#define addr_map_nvdla1_limit_r() (0x158fffffU)
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#define addr_map_mgbe0_base_r() (0x06800000U)
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#define addr_map_mgbe0_limit_r() (0x068fffffU)
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#define addr_map_mgbe1_base_r() (0x06900000U)
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#define addr_map_mgbe1_limit_r() (0x069fffffU)
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#define addr_map_mgbe2_base_r() (0x06a00000U)
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#define addr_map_mgbe2_limit_r() (0x06afffffU)
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#define addr_map_mgbe3_base_r() (0x06b00000U)
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#define addr_map_mgbe3_limit_r() (0x06bfffffU)
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#define addr_map_mcb_base_r() (0x02c10000U)
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#define addr_map_mcb_limit_r() (0x02c1ffffU)
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#define addr_map_mc0_base_r() (0x02c20000U)
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#define addr_map_mc0_limit_r() (0x02c2ffffU)
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#define addr_map_mc1_base_r() (0x02c30000U)
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#define addr_map_mc1_limit_r() (0x02c3ffffU)
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#define addr_map_mc2_base_r() (0x02c40000U)
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#define addr_map_mc2_limit_r() (0x02c4ffffU)
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#define addr_map_mc3_base_r() (0x02c50000U)
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#define addr_map_mc3_limit_r() (0x02c5ffffU)
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#define addr_map_mc4_base_r() (0x02b80000U)
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#define addr_map_mc4_limit_r() (0x02b8ffffU)
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#define addr_map_mc5_base_r() (0x02b90000U)
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#define addr_map_mc5_limit_r() (0x02b9ffffU)
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#define addr_map_mc6_base_r() (0x02ba0000U)
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#define addr_map_mc6_limit_r() (0x02baffffU)
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#define addr_map_mc7_base_r() (0x02bb0000U)
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#define addr_map_mc7_limit_r() (0x02bbffffU)
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#define addr_map_mc8_base_r() (0x01700000U)
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#define addr_map_mc8_limit_r() (0x0170ffffU)
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#define addr_map_mc9_base_r() (0x01710000U)
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#define addr_map_mc9_limit_r() (0x0171ffffU)
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#define addr_map_mc10_base_r() (0x01720000U)
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#define addr_map_mc10_limit_r() (0x0172ffffU)
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#define addr_map_mc11_base_r() (0x01730000U)
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#define addr_map_mc11_limit_r() (0x0173ffffU)
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#define addr_map_mc12_base_r() (0x01740000U)
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#define addr_map_mc12_limit_r() (0x0174ffffU)
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#define addr_map_mc13_base_r() (0x01750000U)
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#define addr_map_mc13_limit_r() (0x0175ffffU)
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#define addr_map_mc14_base_r() (0x01760000U)
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#define addr_map_mc14_limit_r() (0x0176ffffU)
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#define addr_map_mc15_base_r() (0x01770000U)
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#define addr_map_mc15_limit_r() (0x0177ffffU)
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#define addr_map_mss_nvlink_1_base_r() (0x01f20000U)
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#define addr_map_mss_nvlink_1_limit_r() (0x01f3ffffU)
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#define addr_map_mss_nvlink_2_base_r() (0x01f40000U)
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#define addr_map_mss_nvlink_2_limit_r() (0x01f5ffffU)
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#define addr_map_mss_nvlink_3_base_r() (0x01f60000U)
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#define addr_map_mss_nvlink_3_limit_r() (0x01f7ffffU)
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#define addr_map_mss_nvlink_4_base_r() (0x01f80000U)
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#define addr_map_mss_nvlink_4_limit_r() (0x01f9ffffU)
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#define addr_map_mss_nvlink_5_base_r() (0x01fa0000U)
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#define addr_map_mss_nvlink_5_limit_r() (0x01fbffffU)
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#define addr_map_mss_nvlink_6_base_r() (0x01fc0000U)
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#define addr_map_mss_nvlink_6_limit_r() (0x01fdffffU)
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#define addr_map_mss_nvlink_7_base_r() (0x01fe0000U)
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#define addr_map_mss_nvlink_7_limit_r() (0x01ffffffU)
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#define addr_map_mss_nvlink_8_base_r() (0x01e00000U)
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#define addr_map_mss_nvlink_8_limit_r() (0x01e1ffffU)
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#endif
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