mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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0cb6f6b48f
- Generate HWPM hw headers using register generator tool. - Add required hw headers to include/hw/ path - Update driver code to replace static hw defines with hw header definitions. - Remove unused static hw defines. THWPM-39 Change-Id: I57566d51657bb6b22c4b581acd257f1871438adf Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2552741 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/*
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* tegra-soc-hwpm-hw.h:
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* This header contains HW aperture and register info for the Tegra SOC HWPM
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* driver.
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*
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* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TEGRA_SOC_HWPM_HW_H
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#define TEGRA_SOC_HWPM_HW_H
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#include <linux/types.h>
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#include "include/hw/t234/hw_addr_map_soc_hwpm.h"
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#include "include/hw/t234/hw_pmasys_soc_hwpm.h"
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#include "include/hw/t234/hw_pmmsys_soc_hwpm.h"
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/* FIXME: Move enum to DT include file? */
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enum tegra_soc_hwpm_dt_aperture {
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TEGRA_SOC_HWPM_INVALID_DT = -1,
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/* PERFMONs */
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TEGRA_SOC_HWPM_VI0_PERFMON_DT = 0,
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TEGRA_SOC_HWPM_FIRST_PERFMON_DT = TEGRA_SOC_HWPM_VI0_PERFMON_DT,
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TEGRA_SOC_HWPM_VI1_PERFMON_DT = TEGRA_SOC_HWPM_FIRST_PERFMON_DT + 1,
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TEGRA_SOC_HWPM_ISP0_PERFMON_DT,
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TEGRA_SOC_HWPM_VICA0_PERFMON_DT,
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TEGRA_SOC_HWPM_OFAA0_PERFMON_DT,
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TEGRA_SOC_HWPM_PVAV0_PERFMON_DT,
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TEGRA_SOC_HWPM_PVAV1_PERFMON_DT,
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TEGRA_SOC_HWPM_PVAC0_PERFMON_DT,
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TEGRA_SOC_HWPM_NVDLAB0_PERFMON_DT,
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TEGRA_SOC_HWPM_NVDLAB1_PERFMON_DT,
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TEGRA_SOC_HWPM_NVDISPLAY0_PERFMON_DT,
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TEGRA_SOC_HWPM_SYS0_PERFMON_DT,
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TEGRA_SOC_HWPM_MGBE0_PERFMON_DT,
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TEGRA_SOC_HWPM_MGBE1_PERFMON_DT,
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TEGRA_SOC_HWPM_MGBE2_PERFMON_DT,
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TEGRA_SOC_HWPM_MGBE3_PERFMON_DT,
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TEGRA_SOC_HWPM_SCF0_PERFMON_DT,
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TEGRA_SOC_HWPM_NVDECA0_PERFMON_DT,
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TEGRA_SOC_HWPM_NVENCA0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSNVLHSH0_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE0_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE1_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE2_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE3_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE4_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE5_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE6_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE7_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE8_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE9_PERFMON_DT,
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TEGRA_SOC_HWPM_PCIE10_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTA0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTA1_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTA2_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTA3_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTB0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTB1_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTB2_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTB3_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTC0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTC1_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTC2_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTC3_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTD0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTD1_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTD2_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSCHANNELPARTD3_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSHUB0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSHUB1_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSMCFCLIENT0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSMCFMEM0_PERFMON_DT,
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TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT,
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TEGRA_SOC_HWPM_LAST_PERFMON_DT = TEGRA_SOC_HWPM_MSSMCFMEM1_PERFMON_DT,
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/* PMA */
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TEGRA_SOC_HWPM_PMA_DT = TEGRA_SOC_HWPM_LAST_PERFMON_DT + 1,
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/* RTR */
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TEGRA_SOC_HWPM_RTR_DT,
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TEGRA_SOC_HWPM_NUM_DT_APERTURES
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};
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#define IS_PERFMON(idx) (((idx) >= TEGRA_SOC_HWPM_FIRST_PERFMON_DT) && \
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((idx) <= TEGRA_SOC_HWPM_LAST_PERFMON_DT))
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/* RPG_PM Aperture */
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#define PERFMON_BASE(ip_idx) (addr_map_rpg_pm_base_r() + \
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((u32)(ip_idx)) * pmmsys_perdomain_offset_v())
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#define PERFMON_LIMIT(ip_idx) (PERFMON_BASE((ip_idx) + 1) - 1)
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#endif /* TEGRA_SOC_HWPM_HW_H */
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