mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 09:12:05 +03:00
b689a36372
This patch adds support for MSS HUB performance monitoring in the driver. Bug 4287384 Signed-off-by: Vishal Aslot <vaslot@nvidia.com> Change-Id: I35b8c8c9bf1eb8b43dc1baeb10a9701fbd3f2dd9 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2987019 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
347 lines
10 KiB
C
347 lines
10 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm_common.h>
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#include <tegra_hwpm_kmem.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm.h>
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#include <hal/th500/th500_init.h>
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#include <hal/th500/th500_internal.h>
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#include <hal/th500/soc/th500_soc_internal.h>
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static struct tegra_soc_hwpm_chip th500_chip_info = {
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.chip_ips = NULL,
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/* HALs */
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.validate_secondary_hals = th500_hwpm_validate_secondary_hals,
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/* Clocks and resets are configured by UEFI */
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.clk_rst_prepare = NULL,
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.clk_rst_set_rate_enable = NULL,
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.clk_rst_disable = NULL,
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.clk_rst_release = NULL,
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.is_ip_active = th500_hwpm_is_ip_active,
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.is_resource_active = th500_hwpm_is_resource_active,
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.get_rtr_int_idx = th500_get_rtr_int_idx,
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.get_ip_max_idx = th500_get_ip_max_idx,
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.get_rtr_pma_perfmux_ptr = th500_hwpm_soc_get_rtr_pma_perfmux_ptr,
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.extract_ip_ops = th500_hwpm_extract_ip_ops,
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.force_enable_ips = th500_hwpm_force_enable_ips,
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.validate_current_config = th500_hwpm_validate_current_config,
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.get_fs_info = tegra_hwpm_get_fs_info,
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.get_resource_info = tegra_hwpm_get_resource_info,
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.init_prod_values = th500_hwpm_soc_init_prod_values,
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.disable_cg = th500_hwpm_soc_disable_cg,
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.enable_cg = th500_hwpm_soc_enable_cg,
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.reserve_rtr = tegra_hwpm_reserve_rtr,
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.release_rtr = tegra_hwpm_release_rtr,
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.perfmon_enable = th500_hwpm_soc_perfmon_enable,
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.perfmon_disable = th500_hwpm_soc_perfmon_disable,
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.perfmux_disable = tegra_hwpm_perfmux_disable,
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.disable_triggers = th500_hwpm_soc_disable_triggers,
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.check_status = th500_hwpm_soc_check_status,
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.disable_mem_mgmt = th500_hwpm_soc_disable_mem_mgmt,
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.enable_mem_mgmt = th500_hwpm_soc_enable_mem_mgmt,
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.invalidate_mem_config = th500_hwpm_soc_invalidate_mem_config,
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.stream_mem_bytes = th500_hwpm_soc_stream_mem_bytes,
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.disable_pma_streaming = th500_hwpm_soc_disable_pma_streaming,
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.update_mem_bytes_get_ptr = th500_hwpm_soc_update_mem_bytes_get_ptr,
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.get_mem_bytes_put_ptr = th500_hwpm_soc_get_mem_bytes_put_ptr,
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.membuf_overflow_status = th500_hwpm_soc_membuf_overflow_status,
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.get_alist_buf_size = tegra_hwpm_get_alist_buf_size,
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.zero_alist_regs = tegra_hwpm_zero_alist_regs,
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.copy_alist = tegra_hwpm_copy_alist,
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.check_alist = tegra_hwpm_check_alist,
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};
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bool th500_hwpm_validate_secondary_hals(struct tegra_soc_hwpm *hwpm)
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{
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/*
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* Clocks and resets are configured by UEFI
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* So clock-reset HALs are expected to be NULL
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*/
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if (hwpm->active_chip->clk_rst_prepare != NULL) {
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tegra_hwpm_err(hwpm, "clk_rst_prepare HAL initialized");
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return false;
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}
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if (hwpm->active_chip->clk_rst_set_rate_enable != NULL) {
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tegra_hwpm_err(hwpm,
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"clk_rst_set_rate_enable HAL initialized");
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return false;
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}
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if (hwpm->active_chip->clk_rst_disable != NULL) {
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tegra_hwpm_err(hwpm, "clk_rst_disable HAL initialized");
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return false;
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}
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if (hwpm->active_chip->clk_rst_release != NULL) {
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tegra_hwpm_err(hwpm, "clk_rst_release HAL initialized");
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return false;
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}
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return true;
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}
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bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
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u32 ip_enum, u32 *config_ip_index)
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{
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u32 config_ip = TEGRA_HWPM_IP_INACTIVE;
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switch (ip_enum) {
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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case TEGRA_HWPM_IP_MSS_CHANNEL:
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config_ip = TH500_HWPM_IP_MSS_CHANNEL;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
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case TEGRA_HWPM_IP_MSS_HUB:
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config_ip = TH500_HWPM_IP_MSS_HUB;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_CL2)
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case TEGRA_HWPM_IP_CL2:
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config_ip = TH500_HWPM_IP_CL2;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
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case TEGRA_HWPM_IP_MCF_CORE:
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config_ip = TH500_HWPM_IP_MCF_CORE;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
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case TEGRA_HWPM_IP_MCF_CLINK:
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config_ip = TH500_HWPM_IP_MCF_CLINK;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
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case TEGRA_HWPM_IP_MCF_C2C:
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config_ip = TH500_HWPM_IP_MCF_C2C;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC)
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case TEGRA_HWPM_IP_MCF_SOC:
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config_ip = TH500_HWPM_IP_MCF_SOC;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_SMMU)
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case TEGRA_HWPM_IP_SMMU:
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config_ip = TH500_HWPM_IP_SMMU;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
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case TEGRA_HWPM_IP_NVLCTRL:
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config_ip = TH500_HWPM_IP_NVLCTRL;
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break;
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case TEGRA_HWPM_IP_NVLRX:
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config_ip = TH500_HWPM_IP_NVLRX;
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break;
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case TEGRA_HWPM_IP_NVLTX:
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config_ip = TH500_HWPM_IP_NVLTX;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_PCIE)
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case TEGRA_HWPM_IP_PCIE:
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config_ip = TH500_HWPM_IP_PCIE;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C2C)
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case TEGRA_HWPM_IP_C2C:
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config_ip = TH500_HWPM_IP_C2C;
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break;
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#endif
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default:
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tegra_hwpm_err(hwpm,
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"Queried enum tegra_soc_hwpm_ip %d invalid", ip_enum);
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break;
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}
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*config_ip_index = config_ip;
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return (config_ip != TEGRA_HWPM_IP_INACTIVE);
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}
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bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
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u32 res_index, u32 *config_ip_index)
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{
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u32 config_ip = TEGRA_HWPM_IP_INACTIVE;
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switch (res_index) {
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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case TEGRA_HWPM_RESOURCE_MSS_CHANNEL:
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config_ip = TH500_HWPM_IP_MSS_CHANNEL;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
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case TEGRA_HWPM_RESOURCE_MSS_HUB:
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config_ip = TH500_HWPM_IP_MSS_HUB;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_CL2)
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case TEGRA_HWPM_RESOURCE_CL2:
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config_ip = TH500_HWPM_IP_CL2;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
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case TEGRA_HWPM_RESOURCE_MCF_CORE:
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config_ip = TH500_HWPM_IP_MCF_CORE;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
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case TEGRA_HWPM_RESOURCE_MCF_CLINK:
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config_ip = TH500_HWPM_IP_MCF_CLINK;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
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case TEGRA_HWPM_RESOURCE_MCF_C2C:
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config_ip = TH500_HWPM_IP_MCF_C2C;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC)
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case TEGRA_HWPM_RESOURCE_MCF_SOC:
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config_ip = TH500_HWPM_IP_MCF_SOC;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_SMMU)
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case TEGRA_HWPM_RESOURCE_SMMU:
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config_ip = TH500_HWPM_IP_SMMU;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
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case TEGRA_HWPM_RESOURCE_NVLCTRL:
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config_ip = TH500_HWPM_IP_NVLCTRL;
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break;
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case TEGRA_HWPM_RESOURCE_NVLRX:
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config_ip = TH500_HWPM_IP_NVLRX;
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break;
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case TEGRA_HWPM_RESOURCE_NVLTX:
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config_ip = TH500_HWPM_IP_NVLTX;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_PCIE)
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case TEGRA_HWPM_RESOURCE_PCIE:
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config_ip = TH500_HWPM_IP_PCIE;
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break;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C2C)
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case TEGRA_HWPM_RESOURCE_C2C:
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config_ip = TH500_HWPM_IP_C2C;
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break;
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#endif
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case TEGRA_HWPM_RESOURCE_PMA:
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config_ip = TH500_HWPM_IP_PMA;
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break;
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case TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR:
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config_ip = TH500_HWPM_IP_RTR;
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break;
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default:
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tegra_hwpm_err(hwpm, "Queried resource %d invalid",
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res_index);
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break;
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}
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*config_ip_index = config_ip;
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return (config_ip != TEGRA_HWPM_IP_INACTIVE);
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}
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u32 th500_get_rtr_int_idx(void)
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{
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return TH500_HWPM_IP_RTR;
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}
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u32 th500_get_ip_max_idx(void)
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{
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return TH500_HWPM_IP_MAX;
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}
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int th500_hwpm_init_chip_info(struct tegra_soc_hwpm *hwpm)
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{
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struct hwpm_ip **th500_active_ip_info;
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/* Allocate array of pointers to hold active IP structures */
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th500_chip_info.chip_ips = tegra_hwpm_kcalloc(
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hwpm, TH500_HWPM_IP_MAX, sizeof(struct hwpm_ip *));
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/* Add active chip structure link to hwpm super-structure */
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hwpm->active_chip = &th500_chip_info;
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/* Temporary pointer to make below assignments legible */
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th500_active_ip_info = th500_chip_info.chip_ips;
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th500_active_ip_info[TH500_HWPM_IP_PMA] = &th500_hwpm_ip_pma;
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th500_active_ip_info[TH500_HWPM_IP_RTR] = &th500_hwpm_ip_rtr;
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#if defined(CONFIG_TH500_HWPM_IP_MSS_CHANNEL)
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th500_active_ip_info[TH500_HWPM_IP_MSS_CHANNEL] =
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&th500_hwpm_ip_mss_channel;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MSS_HUB)
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th500_active_ip_info[TH500_HWPM_IP_MSS_HUB] =
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&th500_hwpm_ip_mss_hub;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_CL2)
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th500_active_ip_info[TH500_HWPM_IP_CL2] = &th500_hwpm_ip_cl2;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CORE)
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th500_active_ip_info[TH500_HWPM_IP_MCF_CORE] = &th500_hwpm_ip_mcf_core;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_CLINK)
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th500_active_ip_info[TH500_HWPM_IP_MCF_CLINK] =
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&th500_hwpm_ip_mcf_clink;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_C2C)
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th500_active_ip_info[TH500_HWPM_IP_MCF_C2C] =
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&th500_hwpm_ip_mcf_c2c;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_MCF_SOC)
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th500_active_ip_info[TH500_HWPM_IP_MCF_SOC] =
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&th500_hwpm_ip_mcf_soc;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_SMMU)
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th500_active_ip_info[TH500_HWPM_IP_SMMU] = &th500_hwpm_ip_smmu;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C_NVLINK)
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th500_active_ip_info[TH500_HWPM_IP_NVLCTRL] = &th500_hwpm_ip_nvlctrl;
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th500_active_ip_info[TH500_HWPM_IP_NVLRX] = &th500_hwpm_ip_nvlrx;
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th500_active_ip_info[TH500_HWPM_IP_NVLTX] = &th500_hwpm_ip_nvltx;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_PCIE)
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th500_active_ip_info[TH500_HWPM_IP_PCIE] = &th500_hwpm_ip_pcie;
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#endif
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#if defined(CONFIG_TH500_HWPM_IP_C2C)
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th500_active_ip_info[TH500_HWPM_IP_C2C] = &th500_hwpm_ip_c2c;
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#endif
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if (!tegra_hwpm_validate_primary_hals(hwpm)) {
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return -EINVAL;
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}
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return 0;
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}
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