mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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bb4b1def61
Merge the T264 private source code to hwpm common code. This is done after T264 source code can be made public. Bug 4856428 Bug 4943517 Signed-off-by: vasukis <vasukis@nvidia.com> Change-Id: Ie830c5465f32f49978cb465d68785ab3dbaee984 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3219865 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
547 lines
18 KiB
C
547 lines
18 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm_timers.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t264/t264_internal.h>
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#include <hal/t264/ip/rtr/t264_rtr.h>
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#include <hal/t264/hw/t264_pmasys_soc_hwpm.h>
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#include <hal/t264/hw/t264_pmmsys_soc_hwpm.h>
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#define T264_HWPM_ENGINE_INDEX_GPMA0 3U
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#define T264_HWPM_ENGINE_INDEX_GPMA1 4U
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#define T264_HWPM_ENGINE_INDEX_PMA 8U
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int t264_hwpm_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture **rtr_perfmux_ptr,
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struct hwpm_ip_aperture **pma_perfmux_ptr)
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{
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struct tegra_soc_hwpm_chip *active_chip = hwpm->active_chip;
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struct hwpm_ip *chip_ip = active_chip->chip_ips[
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active_chip->get_rtr_int_idx()];
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struct hwpm_ip_inst *ip_inst_rtr = &chip_ip->ip_inst_static_array[
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T264_HWPM_IP_RTR_STATIC_RTR_INST];
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struct hwpm_ip_inst *ip_inst_pma = &chip_ip->ip_inst_static_array[
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T264_HWPM_IP_RTR_STATIC_PMA_INST];
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if (rtr_perfmux_ptr != NULL) {
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*rtr_perfmux_ptr = &ip_inst_rtr->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T264_HWPM_IP_RTR_STATIC_RTR_PERFMUX_INDEX];
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}
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if (pma_perfmux_ptr != NULL) {
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*pma_perfmux_ptr = &ip_inst_pma->element_info[
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TEGRA_HWPM_APERTURE_TYPE_PERFMUX].element_static_array[
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T264_HWPM_IP_RTR_STATIC_PMA_PERFMUX_INDEX];
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}
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return 0;
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}
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int t264_hwpm_check_status(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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struct hwpm_ip_aperture *pma_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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&pma_perfmux);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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/* Check ROUTER state */
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_enginestatus_r(), ®_val);
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hwpm_assert_print(hwpm,
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pmmsys_router_enginestatus_status_v(reg_val) ==
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pmmsys_router_enginestatus_status_empty_v(),
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return -EINVAL, "Router not ready value 0x%x", reg_val);
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/* Check PMA state */
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_status_r(0, 0), ®_val);
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hwpm_assert_print(hwpm,
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(reg_val & pmasys_channel_status_engine_status_m()) ==
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pmasys_channel_status_engine_status_empty_f(),
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return -EINVAL, "PMA not ready value 0x%x", reg_val);
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return 0;
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}
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int t264_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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u32 retries = 10U;
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u32 sleep_msecs = 100U;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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struct hwpm_ip_aperture *pma_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux, &pma_perfmux);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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/* Disable PMA triggers */
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_config_user_r(0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_command_slice_trigger_config_user_pma_pulse_m(),
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pmasys_command_slice_trigger_config_user_pma_pulse_disable_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_config_user_r(0), reg_val);
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/* Reset TRIGGER_START_MASK registers */
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_start_mask0_r(0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_command_slice_trigger_start_mask0_engine_m(),
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pmasys_command_slice_trigger_start_mask0_engine_init_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_start_mask0_r(0), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_start_mask1_r(0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_command_slice_trigger_start_mask1_engine_m(),
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pmasys_command_slice_trigger_start_mask1_engine_init_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_start_mask1_r(0), reg_val);
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/* Reset TRIGGER_STOP_MASK registers */
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_stop_mask0_r(0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_command_slice_trigger_stop_mask0_engine_m(),
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pmasys_command_slice_trigger_stop_mask0_engine_init_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_stop_mask0_r(0), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_stop_mask1_r(0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_command_slice_trigger_stop_mask1_engine_m(),
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pmasys_command_slice_trigger_stop_mask1_engine_init_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_command_slice_trigger_stop_mask1_r(0), reg_val);
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/* Wait for PERFMONs to idle */
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tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux,
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pmmsys_router_enginestatus_r(), ®_val,
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(pmmsys_router_enginestatus_merged_perfmon_status_v(
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reg_val) != 0U),
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"PMMSYS_ROUTER_ENGINESTATUS_PERFMON_STATUS timed out");
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/* Wait for ROUTER to idle */
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tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, rtr_perfmux,
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pmmsys_router_enginestatus_r(), ®_val,
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(pmmsys_router_enginestatus_status_v(reg_val) !=
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pmmsys_router_enginestatus_status_empty_v()),
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"PMMSYS_ROUTER_ENGINESTATUS_STATUS timed out");
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/* Wait for PMA to idle */
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tegra_hwpm_timeout_print(hwpm, retries, sleep_msecs, pma_perfmux,
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pmasys_channel_status_r(0, 0), ®_val,
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((reg_val & pmasys_channel_status_engine_status_m()) !=
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pmasys_channel_status_engine_status_empty_f()),
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"PMASYS_CHANNEL_STATUS timed out");
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return err;
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}
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int t264_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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struct hwpm_ip_aperture *pma_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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&pma_perfmux);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_channel_config_user_r(0,0), ®_val);
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reg_val = set_field(reg_val,
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pmasys_channel_config_user_coalesce_timeout_cycles_m(),
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pmasys_channel_config_user_coalesce_timeout_cycles__prod_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_channel_config_user_r(0,0), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg2_secure_slcg_m(),
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pmasys_profiling_cg2_secure_slcg__prod_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg1_secure_flcg_m(),
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pmasys_profiling_cg1_secure_flcg__prod_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_dg_cg1_secure_flcg_m(),
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pmmsys_router_profiling_dg_cg1_secure_flcg__prod_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_cg1_secure_flcg_m(),
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pmmsys_router_profiling_cg1_secure_flcg__prod_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_perfmon_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_perfmon_cg2_secure_slcg_m(),
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pmmsys_router_perfmon_cg2_secure_slcg__prod_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_perfmon_cg2_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_cg2_secure_slcg_m(),
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pmmsys_router_profiling_cg2_secure_slcg__prod_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg2_secure_r(), reg_val);
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return 0;
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}
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int t264_hwpm_disable_cg(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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struct hwpm_ip_aperture *pma_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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&pma_perfmux);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg2_secure_slcg_m(),
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pmasys_profiling_cg2_secure_slcg_disabled_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg1_secure_flcg_m(),
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pmasys_profiling_cg1_secure_flcg_disabled_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_dg_cg1_secure_flcg_m(),
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pmmsys_router_profiling_dg_cg1_secure_flcg_disabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_cg1_secure_flcg_m(),
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pmmsys_router_profiling_cg1_secure_flcg_disabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_perfmon_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_perfmon_cg2_secure_slcg_m(),
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pmmsys_router_perfmon_cg2_secure_slcg_disabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_perfmon_cg2_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_cg2_secure_slcg_m(),
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pmmsys_router_profiling_cg2_secure_slcg_disabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg2_secure_r(), reg_val);
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return 0;
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}
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int t264_hwpm_enable_cg(struct tegra_soc_hwpm *hwpm)
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{
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int err = 0;
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u32 reg_val = 0U;
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struct hwpm_ip_aperture *rtr_perfmux = NULL;
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struct hwpm_ip_aperture *pma_perfmux = NULL;
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tegra_hwpm_fn(hwpm, " ");
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err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
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&pma_perfmux);
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hwpm_assert_print(hwpm, err == 0, return err,
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"get rtr pma perfmux failed");
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg2_secure_slcg_m(),
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pmasys_profiling_cg2_secure_slcg_enabled_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg2_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val, pmasys_profiling_cg1_secure_flcg_m(),
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pmasys_profiling_cg1_secure_flcg_enabled_f());
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tegra_hwpm_writel(hwpm, pma_perfmux,
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pmasys_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_dg_cg1_secure_flcg_m(),
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pmmsys_router_profiling_dg_cg1_secure_flcg_enabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_dg_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_profiling_cg1_secure_flcg_m(),
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pmmsys_router_profiling_cg1_secure_flcg_enabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
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pmmsys_router_profiling_cg1_secure_r(), reg_val);
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tegra_hwpm_readl(hwpm, rtr_perfmux,
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pmmsys_router_perfmon_cg2_secure_r(), ®_val);
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reg_val = set_field(reg_val,
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pmmsys_router_perfmon_cg2_secure_slcg_m(),
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pmmsys_router_perfmon_cg2_secure_slcg_enabled_f());
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tegra_hwpm_writel(hwpm, rtr_perfmux,
|
|
pmmsys_router_perfmon_cg2_secure_r(), reg_val);
|
|
|
|
tegra_hwpm_readl(hwpm, rtr_perfmux,
|
|
pmmsys_router_profiling_cg2_secure_r(), ®_val);
|
|
reg_val = set_field(reg_val,
|
|
pmmsys_router_profiling_cg2_secure_slcg_m(),
|
|
pmmsys_router_profiling_cg2_secure_slcg_enabled_f());
|
|
tegra_hwpm_writel(hwpm, rtr_perfmux,
|
|
pmmsys_router_profiling_cg2_secure_r(), reg_val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int t264_hwpm_credit_program(struct tegra_soc_hwpm *hwpm,
|
|
u32 *num_credits, u8 cblock_idx, u8 pma_channel_idx,
|
|
uint16_t credit_cmd)
|
|
{
|
|
int err = 0;
|
|
u32 reg_val = 0U;
|
|
struct hwpm_ip_aperture *pma_perfmux = NULL;
|
|
struct hwpm_ip_aperture *rtr_perfmux = NULL;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, &rtr_perfmux,
|
|
&pma_perfmux);
|
|
hwpm_assert_print(hwpm, err == 0, return err,
|
|
"get rtr, pma perfmux failed");
|
|
|
|
switch (credit_cmd) {
|
|
case TEGRA_HWPM_CMD_SET_HS_CREDITS:
|
|
/* Write credits information */
|
|
tegra_hwpm_readl(hwpm, rtr_perfmux,
|
|
pmmsys_user_channel_config_secure_r(
|
|
cblock_idx, pma_channel_idx),
|
|
®_val);
|
|
reg_val = set_field(reg_val,
|
|
pmmsys_user_channel_config_secure_hs_credits_m(),
|
|
*num_credits);
|
|
tegra_hwpm_writel(hwpm, rtr_perfmux,
|
|
pmmsys_user_channel_config_secure_r(
|
|
cblock_idx, pma_channel_idx),
|
|
reg_val);
|
|
break;
|
|
case TEGRA_HWPM_CMD_GET_HS_CREDITS:
|
|
/* Read credits information */
|
|
tegra_hwpm_readl(hwpm, rtr_perfmux,
|
|
pmmsys_user_channel_config_secure_r(
|
|
cblock_idx, pma_channel_idx),
|
|
num_credits);
|
|
break;
|
|
case TEGRA_HWPM_CMD_GET_TOTAL_HS_CREDITS:
|
|
/* read the total HS Credits */
|
|
tegra_hwpm_readl(hwpm, pma_perfmux,
|
|
pmasys_streaming_capabilities1_r(), ®_val);
|
|
*num_credits = pmasys_streaming_capabilities1_total_credits_v(
|
|
reg_val);
|
|
break;
|
|
case TEGRA_HWPM_CMD_GET_CHIPLET_HS_CREDITS_POOL:
|
|
/* Defined for future chips */
|
|
tegra_hwpm_err(hwpm,
|
|
"TEGRA_SOC_HWPM_CMD_GET_CHIPLET_HS_CREDIT_POOL"
|
|
" not supported");
|
|
err = -EINVAL;
|
|
break;
|
|
case TEGRA_HWPM_CMD_GET_HS_CREDITS_MAPPING:
|
|
/* Defined for future chips */
|
|
tegra_hwpm_err(hwpm,
|
|
"TEGRA_SOC_HWPM_CMD_GET_HS_CREDIT_MAPPING"
|
|
" not supported");
|
|
err = -EINVAL;
|
|
break;
|
|
default:
|
|
tegra_hwpm_err(hwpm, "Invalid Credit Programming State (%d)",
|
|
credit_cmd);
|
|
err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
int t264_hwpm_setup_trigger(struct tegra_soc_hwpm *hwpm,
|
|
u8 enable_cross_trigger, u8 session_type)
|
|
{
|
|
int err = 0;
|
|
u32 trigger_mask_secure0 = 0U;
|
|
u32 record_select_secure = 0U;
|
|
struct hwpm_ip_aperture *pma_perfmux = NULL;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
err = hwpm->active_chip->get_rtr_pma_perfmux_ptr(hwpm, NULL,
|
|
&pma_perfmux);
|
|
hwpm_assert_print(hwpm, err == 0, return err,
|
|
"get pma perfmux failed");
|
|
|
|
/*
|
|
* Case 1: profiler, cross-trigger enabled, GPU->SoC
|
|
* - Action: enable incoming start-stop trigger from GPU PMA
|
|
* - GPU PMA Action: enable outgoing trigger from GPU PMA,
|
|
* trigger type doesn't matter on GPU side
|
|
*
|
|
* Case 2: sampler, cross-trigger enabled, GPU->SoC
|
|
* - Action: enable incoming periodic trigger from GPU PMA
|
|
* - GPU PMA Action: enable outgoing trigger from GPU PMA,
|
|
* trigger type doesn't matter on GPU side
|
|
*
|
|
* Case 3: profiler, cross-trigger enabled, SoC->GPU
|
|
* - Action: enable outgoing trigger from SoC PMA,
|
|
* trigger type doesn't matter on SoC side
|
|
* - GPU PMA Action: configure incoming start-stop trigger from SoC PMA
|
|
*
|
|
* Case 4: sampler, cross-trigger enabled, SoC->GPU
|
|
* - Action: enable outgoing trigger from SoC PMA,
|
|
* trigger type doesn't matter on SoC side
|
|
* - GPU PMA Action: configure incoming periodic trigger from SoC PMA
|
|
*
|
|
* Case 5: profiler, cross-trigger disabled
|
|
* - Action: enable own trigger from SoC PMA,
|
|
* trigger type doesn't matter
|
|
* - GPU PMA Action: enable own trigger from GPU PMA,
|
|
* trigger type doesn't matter)
|
|
*
|
|
* Case 6: sampler, cross-trigger disabled
|
|
* - Action: enable own trigger from SoC PMA,
|
|
* trigger type doesn't matter
|
|
* - GPU PMA Action: enable own trigger from GPU PMA,
|
|
* trigger type doesn't matter
|
|
*/
|
|
if (!enable_cross_trigger) {
|
|
/*
|
|
* Handle Case-3 to Case-6
|
|
*/
|
|
trigger_mask_secure0 = BIT(T264_HWPM_ENGINE_INDEX_PMA);
|
|
record_select_secure = T264_HWPM_ENGINE_INDEX_PMA;
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_trigger_mask_secure0_r(0),
|
|
trigger_mask_secure0);
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_record_select_secure_r(0),
|
|
record_select_secure);
|
|
|
|
return err;
|
|
}
|
|
|
|
switch (session_type) {
|
|
case TEGRA_HWPM_CMD_PERIODIC_SESSION:
|
|
/*
|
|
* Handle Case-1
|
|
*/
|
|
trigger_mask_secure0 = BIT(T264_HWPM_ENGINE_INDEX_GPMA1);
|
|
record_select_secure = T264_HWPM_ENGINE_INDEX_GPMA1;
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_trigger_mask_secure0_r(0),
|
|
trigger_mask_secure0);
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_record_select_secure_r(0),
|
|
record_select_secure);
|
|
break;
|
|
case TEGRA_HWPM_CMD_START_STOP_SESSION:
|
|
/*
|
|
* Handle Case-2
|
|
*/
|
|
trigger_mask_secure0 = BIT(T264_HWPM_ENGINE_INDEX_GPMA0);
|
|
record_select_secure = T264_HWPM_ENGINE_INDEX_GPMA0;
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_trigger_mask_secure0_r(0),
|
|
trigger_mask_secure0);
|
|
tegra_hwpm_writel(hwpm, pma_perfmux,
|
|
pmasys_command_slice_record_select_secure_r(0),
|
|
record_select_secure);
|
|
break;
|
|
case TEGRA_HWPM_CMD_INVALID_SESSION:
|
|
default:
|
|
tegra_hwpm_err(hwpm, "Invalid Session type");
|
|
err = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return err;
|
|
}
|