mirror of
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bb4b1def61
Merge the T264 private source code to hwpm common code. This is done after T264 source code can be made public. Bug 4856428 Bug 4943517 Signed-off-by: vasukis <vasukis@nvidia.com> Change-Id: Ie830c5465f32f49978cb465d68785ab3dbaee984 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3219865 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
116 lines
4.8 KiB
C
116 lines
4.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef T264_HWPM_INTERNAL_H
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#define T264_HWPM_INTERNAL_H
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#include <hal/t264/ip/vic/t264_vic.h>
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#include <hal/t264/ip/pva/t264_pva.h>
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#include <hal/t264/ip/mss_channel/t264_mss_channel.h>
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#include <hal/t264/ip/mss_hubs/t264_mss_hubs.h>
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#include <hal/t264/ip/ocu/t264_ocu.h>
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#include <hal/t264/ip/smmu/t264_smmu.h>
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#include <hal/t264/ip/ucf_msw/t264_ucf_msw.h>
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#include <hal/t264/ip/ucf_psw/t264_ucf_psw.h>
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#include <hal/t264/ip/ucf_csw/t264_ucf_csw.h>
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#include <hal/t264/ip/cpu/t264_cpu.h>
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#include <hal/t264/ip/pma/t264_pma.h>
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#include <hal/t264/ip/rtr/t264_rtr.h>
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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#define DEFINE_SOC_HWPM_ACTIVE_IP(name) name
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#define T264_HWPM_ACTIVE_IP_MAX T264_HWPM_IP_MAX
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#define T264_ACTIVE_IPS \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_PMA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_RTR) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_VIC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_PVA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MSS_CHANNEL) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MSS_HUBS) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_OCU) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_SMMU) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_MSW) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_PSW) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_UCF_CSW) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_CPU) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T264_HWPM_ACTIVE_IP_MAX)
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enum t264_hwpm_active_ips {
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T264_ACTIVE_IPS
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};
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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enum tegra_soc_hwpm_ip;
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enum tegra_soc_hwpm_resource;
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struct tegra_soc_hwpm;
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struct hwpm_ip_aperture;
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bool t264_hwpm_validate_secondary_hals(struct tegra_soc_hwpm *hwpm);
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bool t264_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
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u32 ip_enum, u32 *config_ip_index);
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bool t264_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
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u32 res_enum, u32 *config_ip_index);
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u32 t264_get_rtr_int_idx(void);
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u32 t264_get_ip_max_idx(void);
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int t264_hwpm_get_rtr_pma_perfmux_ptr(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture **rtr_perfmux_ptr,
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struct hwpm_ip_aperture **pma_perfmux_ptr);
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int t264_hwpm_check_status(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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u32 resource_enum, u64 base_address,
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struct tegra_hwpm_ip_ops *ip_ops, bool available);
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int t264_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_credit_program(struct tegra_soc_hwpm *hwpm,
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u32 *num_credits, u8 cblock_idx, u8 pma_channel_idx,
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uint16_t credit_cmd);
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int t264_hwpm_setup_trigger(struct tegra_soc_hwpm *hwpm,
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u8 enable_cross_trigger, u8 session_type);
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int t264_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon);
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int t264_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon);
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int t264_hwpm_disable_cg(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_enable_cg(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm);
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int t264_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
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u64 mem_bump);
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int t264_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm,
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u64 *mem_head_ptr);
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int t264_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm,
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u32 *overflow_status);
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#endif /* T264_HWPM_INTERNAL_H */
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