mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-22 09:12:05 +03:00
bc6fdf1f18
This patch adds support for C-NVLINK performance monitoring in the driver. C-NVLINK consists of RX, TX, and CTRL apertures, each with its own perfmux signals and perfmons. So this patch breaks them up into three sets of perfmux-perfmon data structures. Bug 4287384 Signed-off-by: Vishal Aslot <vaslot@nvidia.com> Change-Id: Id8be4c965018125765f75a7b8bc8ab809bb7f976 Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2999166 GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com> Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
447 lines
12 KiB
C
447 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/slab.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_kmem.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <os/linux/ip_utils.h>
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#include <os/linux/driver.h>
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struct platform_device *tegra_soc_hwpm_pdev;
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struct hwpm_ip_register_list *ip_register_list_head;
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#define REGISTER_IP true
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#define UNREGISTER_IP false
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static u32 tegra_hwpm_translate_soc_hwpm_ip(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_ip ip_enum)
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{
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u32 ip_enum_idx = TEGRA_HWPM_IP_INACTIVE;
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switch (ip_enum) {
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case TEGRA_SOC_HWPM_IP_VI:
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ip_enum_idx = TEGRA_HWPM_IP_VI;
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break;
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case TEGRA_SOC_HWPM_IP_ISP:
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ip_enum_idx = TEGRA_HWPM_IP_ISP;
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break;
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case TEGRA_SOC_HWPM_IP_VIC:
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ip_enum_idx = TEGRA_HWPM_IP_VIC;
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break;
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case TEGRA_SOC_HWPM_IP_OFA:
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ip_enum_idx = TEGRA_HWPM_IP_OFA;
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break;
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case TEGRA_SOC_HWPM_IP_PVA:
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ip_enum_idx = TEGRA_HWPM_IP_PVA;
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break;
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case TEGRA_SOC_HWPM_IP_NVDLA:
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ip_enum_idx = TEGRA_HWPM_IP_NVDLA;
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break;
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case TEGRA_SOC_HWPM_IP_MGBE:
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ip_enum_idx = TEGRA_HWPM_IP_MGBE;
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break;
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case TEGRA_SOC_HWPM_IP_SCF:
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ip_enum_idx = TEGRA_HWPM_IP_SCF;
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break;
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case TEGRA_SOC_HWPM_IP_NVDEC:
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ip_enum_idx = TEGRA_HWPM_IP_NVDEC;
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break;
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case TEGRA_SOC_HWPM_IP_NVENC:
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ip_enum_idx = TEGRA_HWPM_IP_NVENC;
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break;
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case TEGRA_SOC_HWPM_IP_PCIE:
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ip_enum_idx = TEGRA_HWPM_IP_PCIE;
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break;
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case TEGRA_SOC_HWPM_IP_DISPLAY:
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ip_enum_idx = TEGRA_HWPM_IP_DISPLAY;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_CHANNEL:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_CHANNEL;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_GPU_HUB:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_GPU_HUB;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_ISO_NISO_HUBS:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_ISO_NISO_HUBS;
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break;
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case TEGRA_SOC_HWPM_IP_MSS_MCF:
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ip_enum_idx = TEGRA_HWPM_IP_MSS_MCF;
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break;
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case TEGRA_SOC_HWPM_IP_APE:
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ip_enum_idx = TEGRA_HWPM_IP_APE;
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break;
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case TEGRA_SOC_HWPM_IP_C2C:
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ip_enum_idx = TEGRA_HWPM_IP_C2C;
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break;
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case TEGRA_SOC_HWPM_IP_SMMU:
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ip_enum_idx = TEGRA_HWPM_IP_SMMU;
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break;
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case TEGRA_SOC_HWPM_IP_CL2:
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ip_enum_idx = TEGRA_HWPM_IP_CL2;
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break;
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case TEGRA_SOC_HWPM_IP_NVLCTRL:
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ip_enum_idx = TEGRA_HWPM_IP_NVLCTRL;
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break;
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case TEGRA_SOC_HWPM_IP_NVLRX:
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ip_enum_idx = TEGRA_HWPM_IP_NVLRX;
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break;
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case TEGRA_SOC_HWPM_IP_NVLTX:
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ip_enum_idx = TEGRA_HWPM_IP_NVLTX;
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break;
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default:
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tegra_hwpm_err(hwpm,
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"Queried enum tegra_soc_hwpm_ip %d is invalid",
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ip_enum);
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break;
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}
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return ip_enum_idx;
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}
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int tegra_hwpm_obtain_floorsweep_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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for (i = 0U; i < fs_info->num_queries; i++) {
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ret = hwpm->active_chip->get_fs_info(hwpm,
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tegra_hwpm_translate_soc_hwpm_ip(
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hwpm, fs_info->ip_fsinfo[i].ip),
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&fs_info->ip_fsinfo[i].ip_inst_mask,
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&fs_info->ip_fsinfo[i].status);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Failed to get fs_info query %d", i);
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}
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_floorsweep_info,
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"Query %d: tegra_soc_hwpm_ip %d: ip_status: %d"
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" inst_mask 0x%llx",
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i, fs_info->ip_fsinfo[i].ip,
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fs_info->ip_fsinfo[i].status,
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fs_info->ip_fsinfo[i].ip_inst_mask);
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}
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return ret;
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}
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u32 tegra_hwpm_translate_soc_hwpm_resource(struct tegra_soc_hwpm *hwpm,
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enum tegra_soc_hwpm_resource res_enum)
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{
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u32 res_enum_idx = TEGRA_HWPM_IP_INACTIVE;
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switch (res_enum) {
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case TEGRA_SOC_HWPM_RESOURCE_VI:
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res_enum_idx = TEGRA_HWPM_RESOURCE_VI;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_ISP:
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res_enum_idx = TEGRA_HWPM_RESOURCE_ISP;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_VIC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_VIC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_OFA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_OFA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PVA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PVA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVDLA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVDLA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MGBE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MGBE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_SCF:
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res_enum_idx = TEGRA_HWPM_RESOURCE_SCF;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVDEC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVDEC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVENC:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVENC;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PCIE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PCIE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_DISPLAY:
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res_enum_idx = TEGRA_HWPM_RESOURCE_DISPLAY;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_CHANNEL:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_CHANNEL;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_GPU_HUB:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_GPU_HUB;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_ISO_NISO_HUBS:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_ISO_NISO_HUBS;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_MSS_MCF:
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res_enum_idx = TEGRA_HWPM_RESOURCE_MSS_MCF;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_PMA:
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res_enum_idx = TEGRA_HWPM_RESOURCE_PMA;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CMD_SLICE_RTR:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CMD_SLICE_RTR;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_APE:
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res_enum_idx = TEGRA_HWPM_RESOURCE_APE;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_C2C:
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res_enum_idx = TEGRA_HWPM_RESOURCE_C2C;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_SMMU:
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res_enum_idx = TEGRA_HWPM_RESOURCE_SMMU;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_CL2:
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res_enum_idx = TEGRA_HWPM_RESOURCE_CL2;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLCTRL:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLCTRL;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLRX:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLRX;
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break;
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case TEGRA_SOC_HWPM_RESOURCE_NVLTX:
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res_enum_idx = TEGRA_HWPM_RESOURCE_NVLTX;
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break;
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default:
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tegra_hwpm_err(hwpm,
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"Queried enum tegra_soc_hwpm_resource %d is invalid",
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res_enum);
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break;
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}
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return res_enum_idx;
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}
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int tegra_hwpm_obtain_resource_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_resource_info *rsrc_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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for (i = 0U; i < rsrc_info->num_queries; i++) {
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ret = hwpm->active_chip->get_resource_info(
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hwpm, tegra_hwpm_translate_soc_hwpm_resource(
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hwpm, rsrc_info->resource_info[i].resource),
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&rsrc_info->resource_info[i].status);
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if (ret < 0) {
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/* Print error for debug purpose. */
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tegra_hwpm_err(hwpm, "Failed to get rsrc_info");
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}
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_resource_info,
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"Query %d: resource %d: status: %d",
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i, rsrc_info->resource_info[i].resource,
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rsrc_info->resource_info[i].status);
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}
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return ret;
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}
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static int tegra_hwpm_record_ip_ops(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_ops *soc_ip_ops, bool available)
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{
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struct tegra_hwpm_ip_ops ip_ops;
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tegra_hwpm_fn(hwpm, " ");
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ip_ops.ip_dev = soc_ip_ops->ip_dev;
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ip_ops.hwpm_ip_pm = soc_ip_ops->hwpm_ip_pm;
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ip_ops.hwpm_ip_reg_op = soc_ip_ops->hwpm_ip_reg_op;
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if (soc_ip_ops->resource_enum >= TERGA_SOC_HWPM_NUM_RESOURCES) {
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tegra_hwpm_err(hwpm, "resource enum %d out of scope",
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soc_ip_ops->resource_enum);
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return -EINVAL;
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}
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return hwpm->active_chip->extract_ip_ops(hwpm,
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tegra_hwpm_translate_soc_hwpm_resource(hwpm,
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(enum tegra_soc_hwpm_resource)soc_ip_ops->resource_enum),
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soc_ip_ops->ip_base_address,
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&ip_ops, available);
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}
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int tegra_hwpm_complete_ip_register_impl(struct tegra_soc_hwpm *hwpm)
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{
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int ret = 0;
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struct hwpm_ip_register_list *node = ip_register_list_head;
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tegra_hwpm_fn(hwpm, " ");
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while (node != NULL) {
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ret = tegra_hwpm_record_ip_ops(hwpm, &node->ip_ops, REGISTER_IP);
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if (ret != 0) {
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tegra_hwpm_err(hwpm,
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"Resource enum %d extract IP ops failed",
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node->ip_ops.resource_enum);
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return ret;
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}
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node = node->next;
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}
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return ret;
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}
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static int tegra_hwpm_alloc_ip_register_list_node(
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struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops,
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struct hwpm_ip_register_list **node_ptr)
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{
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struct hwpm_ip_register_list *new_node = NULL;
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new_node = tegra_hwpm_kzalloc(NULL,
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sizeof(struct hwpm_ip_register_list));
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if (new_node == NULL) {
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tegra_hwpm_err(NULL,
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"struct hwpm_ip_register_list node allocation failed");
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return -ENOMEM;
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}
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new_node->next = NULL;
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/* Copy given ip register details to node */
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memcpy(&new_node->ip_ops, hwpm_ip_ops,
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sizeof(struct tegra_soc_hwpm_ip_ops));
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(*node_ptr) = new_node;
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return 0;
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}
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static int tegra_hwpm_note_ip_register(
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struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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int err = 0;
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struct hwpm_ip_register_list *node;
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if (ip_register_list_head == NULL) {
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err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
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&ip_register_list_head);
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if (err != 0) {
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tegra_hwpm_err(NULL,
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"failed to note ip registration");
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return err;
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}
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} else {
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node = ip_register_list_head;
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while (node->next != NULL) {
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node = node->next;
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}
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err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
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&node->next);
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if (err != 0) {
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tegra_hwpm_err(NULL,
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"failed to note ip registration");
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return err;
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}
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}
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return err;
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}
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void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (hwpm_ip_ops == NULL) {
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tegra_hwpm_err(NULL, "IP details missing");
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return;
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}
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
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"Noting IP 0x%llx register request",
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hwpm_ip_ops->ip_base_address);
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ret = tegra_hwpm_note_ip_register(hwpm_ip_ops);
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if (ret != 0) {
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tegra_hwpm_err(NULL,
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"Couldn't save IP register details");
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return;
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}
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to register is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
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"Register IP 0x%llx", hwpm_ip_ops->ip_base_address);
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ret = tegra_hwpm_record_ip_ops(hwpm, hwpm_ip_ops, REGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
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hwpm_ip_ops->resource_enum);
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}
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}
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}
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EXPORT_SYMBOL(tegra_soc_hwpm_ip_register);
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void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (hwpm_ip_ops == NULL) {
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tegra_hwpm_err(NULL, "IP details missing");
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return;
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}
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
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"HWPM device not available");
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to unregister is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info | hwpm_dbg_ip_register,
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"Unregister IP 0x%llx", hwpm_ip_ops->ip_base_address);
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ret = tegra_hwpm_record_ip_ops(hwpm, hwpm_ip_ops, UNREGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
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hwpm_ip_ops->resource_enum);
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}
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}
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}
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EXPORT_SYMBOL(tegra_soc_hwpm_ip_unregister);
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void tegra_hwpm_release_ip_register_node(struct tegra_soc_hwpm *hwpm)
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{
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struct hwpm_ip_register_list *node = ip_register_list_head;
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struct hwpm_ip_register_list *tmp_node = NULL;
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tegra_hwpm_fn(hwpm, " ");
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while (node != NULL) {
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tmp_node = node;
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node = tmp_node->next;
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tegra_hwpm_kfree(hwpm, tmp_node);
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}
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}
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