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8b861518c4
Modify OS agnostic files in common, hal and include folder to use MIT license. This will allow the files to be shared between different OSes. Modify OS specific files in os/linux and uapi folders to add SPDX identifier for GPLv2. Jira THWPM-69 Change-Id: I4fef142354a46fc23b67616204ccf0712a99caec Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2797453 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
118 lines
5.0 KiB
C
118 lines
5.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef T234_HWPM_INTERNAL_H
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#define T234_HWPM_INTERNAL_H
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#include <hal/t234/ip/vi/t234_vi.h>
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#include <hal/t234/ip/isp/t234_isp.h>
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#include <hal/t234/ip/vic/t234_vic.h>
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#include <hal/t234/ip/ofa/t234_ofa.h>
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#include <hal/t234/ip/pva/t234_pva.h>
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#include <hal/t234/ip/nvdla/t234_nvdla.h>
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#include <hal/t234/ip/mgbe/t234_mgbe.h>
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#include <hal/t234/ip/scf/t234_scf.h>
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#include <hal/t234/ip/nvdec/t234_nvdec.h>
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#include <hal/t234/ip/nvenc/t234_nvenc.h>
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#include <hal/t234/ip/pcie/t234_pcie.h>
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#include <hal/t234/ip/display/t234_display.h>
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#include <hal/t234/ip/mss_channel/t234_mss_channel.h>
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#include <hal/t234/ip/mss_gpu_hub/t234_mss_gpu_hub.h>
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#include <hal/t234/ip/mss_iso_niso_hubs/t234_mss_iso_niso_hubs.h>
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#include <hal/t234/ip/mss_mcf/t234_mss_mcf.h>
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#include <hal/t234/ip/pma/t234_pma.h>
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#include <hal/t234/ip/rtr/t234_rtr.h>
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#define T234_HWPM_ACTIVE_IP_MAX T234_HWPM_IP_MAX
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#define T234_ACTIVE_IPS \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_PMA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_RTR) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VI) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_ISP) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_VIC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_OFA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_PVA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_NVDLA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MGBE) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_SCF) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_NVDEC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_NVENC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_PCIE) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_DISPLAY) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MSS_CHANNEL) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MSS_GPU_HUB) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MSS_ISO_NISO_HUBS) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MSS_MCF) \
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DEFINE_SOC_HWPM_ACTIVE_IP(T234_HWPM_ACTIVE_IP_MAX)
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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#define DEFINE_SOC_HWPM_ACTIVE_IP(name) name
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enum t234_hwpm_active_ips {
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T234_ACTIVE_IPS
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};
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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enum tegra_soc_hwpm_ip;
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enum tegra_soc_hwpm_resource;
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struct tegra_soc_hwpm;
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struct hwpm_ip_aperture;
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bool t234_hwpm_validate_secondary_hals(struct tegra_soc_hwpm *hwpm);
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bool t234_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
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u32 ip_enum, u32 *config_ip_index);
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bool t234_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
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u32 res_enum, u32 *config_ip_index);
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u32 t234_get_rtr_int_idx(struct tegra_soc_hwpm *hwpm);
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u32 t234_get_ip_max_idx(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_extract_ip_ops(struct tegra_soc_hwpm *hwpm,
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u32 resource_enum, u64 base_address,
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struct tegra_hwpm_ip_ops *ip_ops, bool available);
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int t234_hwpm_force_enable_ips(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_validate_current_config(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_init_prod_values(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_disable_cg(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_enable_cg(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_check_status(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon);
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int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon);
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int t234_hwpm_disable_mem_mgmt(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_enable_mem_mgmt(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_invalidate_mem_config(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_stream_mem_bytes(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_disable_pma_streaming(struct tegra_soc_hwpm *hwpm);
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int t234_hwpm_update_mem_bytes_get_ptr(struct tegra_soc_hwpm *hwpm,
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u64 mem_bump);
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u64 t234_hwpm_get_mem_bytes_put_ptr(struct tegra_soc_hwpm *hwpm);
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bool t234_hwpm_membuf_overflow_status(struct tegra_soc_hwpm *hwpm);
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#endif /* T234_HWPM_INTERNAL_H */
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