mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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26bd5451c2
- Modify the OS common code to be used by HWPM resource manager in QNX. - Add dev_name and fd fields in IP files - Typecast variables to unsigned long long where ever they are printed with %llx. Jira THWPM-54 Change-Id: Ie3696f5dab03dddf30ae6939525ef8f999260d5d Signed-off-by: vasukis <vasukis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2901186 Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_internal.h>
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#include <hal/t234/hw/t234_pmasys_soc_hwpm.h>
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#include <hal/t234/hw/t234_pmmsys_soc_hwpm.h>
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int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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/* Enable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_bind,
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"Enabling PERFMON(0x%llx - 0x%llx)",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_sys0_enginestatus_enable_m(),
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pmmsys_sys0_enginestatus_enable_out_f());
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err = tegra_hwpm_writel(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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if (perfmon->element_type == HWPM_ELEMENT_PERFMUX) {
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/*
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* Since HWPM elements use perfmon functions,
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* skip disabling HWPM PERFMUX elements
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*/
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return 0;
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}
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/* Disable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_release_resource,
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"Disabling PERFMON(0x%llx - 0x%llx)",
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(unsigned long long)perfmon->start_abs_pa,
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(unsigned long long)perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_control_mode_m(),
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pmmsys_control_mode_disable_f());
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err = tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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