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- Many HWPM functions are performed on all apertures of all instances of all IPs. Define below resource utility functions to perform a task on all IPs, instances and apertures: - tegra_hwpm_func_all_IPs - tegra_hwpm_func_single_ip - tegra_hwpm_func_all_instance - tegra_hwpm_func_single_instance - tegra_hwpm_func_all_perfmuxes - tegra_hwpm_func_all_perfmons - tegra_hwpm_func_single_aperture - Modify below functions to use above mentioned utility functions: - get allowlist size - combine allowlist - reserve resources - bind resources - release resources This will make code more legible and maintainable. This patch also defines new function that validates all HAL initializations for the chip. Jira THWPM-41 Change-Id: Icaeba4d94187b97022c0a6626584e7d61ab6d0e4 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2705524 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
175 lines
4.4 KiB
C
175 lines
4.4 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/slab.h>
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#include <soc/tegra/fuse.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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struct platform_device *tegra_soc_hwpm_pdev;
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struct hwpm_ip_register_list *ip_register_list_head;
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#define REGISTER_IP true
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#define UNREGISTER_IP false
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static int tegra_hwpm_alloc_ip_register_list_node(
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struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops,
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struct hwpm_ip_register_list **node_ptr)
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{
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struct hwpm_ip_register_list *new_node = NULL;
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new_node = kzalloc(sizeof(struct hwpm_ip_register_list), GFP_KERNEL);
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if (new_node == NULL) {
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tegra_hwpm_err(NULL,
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"struct hwpm_ip_register_list node allocation failed");
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return -ENOMEM;
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}
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new_node->next = NULL;
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/* Copy given ip register details to node */
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memcpy(&new_node->ip_ops, hwpm_ip_ops,
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sizeof(struct tegra_soc_hwpm_ip_ops));
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(*node_ptr) = new_node;
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return 0;
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}
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static int tegra_hwpm_note_ip_register(
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struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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int err = 0;
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struct hwpm_ip_register_list *node;
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if (ip_register_list_head == NULL) {
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err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
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&ip_register_list_head);
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if (err != 0) {
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tegra_hwpm_err(NULL,
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"failed to note ip registration");
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return err;
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}
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} else {
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node = ip_register_list_head;
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while (node->next != NULL) {
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node = node->next;
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}
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err = tegra_hwpm_alloc_ip_register_list_node(hwpm_ip_ops,
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&node->next);
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if (err != 0) {
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tegra_hwpm_err(NULL,
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"failed to note ip registration");
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return err;
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}
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}
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return err;
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}
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void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (hwpm_ip_ops == NULL) {
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tegra_hwpm_err(NULL, "IP details missing");
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return;
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}
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if (tegra_soc_hwpm_pdev == NULL) {
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ret = tegra_hwpm_note_ip_register(hwpm_ip_ops);
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if (ret != 0) {
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tegra_hwpm_err(NULL,
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"Couldn't save IP register details");
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return;
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}
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to register is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Register IP 0x%llx", hwpm_ip_ops->ip_base_address);
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ret = hwpm->active_chip->extract_ip_ops(hwpm,
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hwpm_ip_ops, REGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
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hwpm_ip_ops->ip_index);
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}
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}
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}
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void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
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{
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struct tegra_soc_hwpm *hwpm = NULL;
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int ret = 0;
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if (hwpm_ip_ops == NULL) {
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tegra_hwpm_err(NULL, "IP details missing");
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return;
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}
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if (tegra_soc_hwpm_pdev == NULL) {
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tegra_hwpm_dbg(hwpm, hwpm_info, "HWPM device not available");
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} else {
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if (hwpm_ip_ops->ip_dev == NULL) {
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tegra_hwpm_err(hwpm, "IP dev to unregister is NULL");
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return;
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}
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hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
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tegra_hwpm_dbg(hwpm, hwpm_info,
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"Unregister IP 0x%llx", hwpm_ip_ops->ip_base_address);
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ret = hwpm->active_chip->extract_ip_ops(hwpm,
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hwpm_ip_ops, UNREGISTER_IP);
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if (ret < 0) {
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tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
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hwpm_ip_ops->ip_index);
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}
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}
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}
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int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
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{
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int ret = 0;
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u32 i = 0U;
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tegra_hwpm_fn(hwpm, " ");
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for (i = 0U; i < fs_info->num_queries; i++) {
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ret = hwpm->active_chip->get_fs_info(
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hwpm, (u32)fs_info->ip_fsinfo[i].ip_type,
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&fs_info->ip_fsinfo[i].ip_inst_mask,
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&fs_info->ip_fsinfo[i].status);
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if (ret < 0) {
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/* Print error for debug purpose. */
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tegra_hwpm_err(hwpm, "Failed to get fs_info");
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}
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tegra_hwpm_dbg(hwpm, hwpm_verbose,
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"Query %d: ip_type %d: ip_status: %d inst_mask 0x%llx",
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i, fs_info->ip_fsinfo[i].ip_type,
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fs_info->ip_fsinfo[i].status,
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fs_info->ip_fsinfo[i].ip_inst_mask);
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}
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return ret;
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}
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