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git://nv-tegra.nvidia.com/linux-hwpm.git
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ea6b4bcc07
Modify the OS common code to be used by HWPM resource manager on QNX. Jira THWPM-54 Change-Id: I5e0e8258eececea1526e50e2efe18c79765b86b0 Signed-off-by: vasukis <vasukis@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2870342 Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Yogesh Solanke <ysolanke@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com>
100 lines
3.0 KiB
C
100 lines
3.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TEGRA_HWPM_SOC_H
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#define TEGRA_HWPM_SOC_H
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#if defined(CONFIG_TEGRA_HWPM_OOT)
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#define CHIP_ID_UNKNOWN 0x0U
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#define CHIP_ID_REV_UNKNOWN 0x0U
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#define PLAT_SI 0x0
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#define PLAT_PRE_SI_QT 0x1
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#define PLAT_PRE_SI_VDK 0x8
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#define PLAT_PRE_SI_VSP 0x9
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#define PLAT_INVALID 0xF
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#define TEGRA_FUSE_PRODUCTION_MODE 0x0
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struct hwpm_soc_chip_info {
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u32 chip_id;
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u32 chip_id_rev;
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u32 platform;
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};
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#endif
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#ifdef __KERNEL__
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#include <os/linux/soc_utils.h>
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#else
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#include <os/qnx/soc_utils.h>
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#define CHIP_ID_UNKNOWN 0x0U
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#define CHIP_ID_REV_UNKNOWN 0x0U
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#define PLAT_SI 0x0
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#define PLAT_PRE_SI_QT 0x1
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#define PLAT_PRE_SI_VDK 0x8
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#define PLAT_PRE_SI_VSP 0x9
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#define PLAT_INVALID 0xF
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#define TEGRA_FUSE_PRODUCTION_MODE 0x0
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struct hwpm_soc_chip_info {
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u32 chip_id;
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u32 chip_id_rev;
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u32 platform;
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};
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#endif
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#define tegra_hwpm_get_chip_id() \
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tegra_hwpm_get_chip_id_impl()
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#define tegra_hwpm_get_major_rev() \
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tegra_hwpm_get_major_rev_impl()
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#define tegra_hwpm_chip_get_revision() \
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tegra_hwpm_chip_get_revision_impl()
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#define tegra_hwpm_get_platform() \
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tegra_hwpm_get_platform_impl()
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#define tegra_hwpm_is_platform_simulation() \
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tegra_hwpm_is_platform_simulation_impl()
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#define tegra_hwpm_is_platform_vsp() \
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tegra_hwpm_is_platform_vsp_impl()
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#define tegra_hwpm_is_platform_silicon() \
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tegra_hwpm_is_platform_silicon_impl()
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#define tegra_hwpm_is_hypervisor_mode() \
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tegra_hwpm_is_hypervisor_mode_impl()
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#define tegra_hwpm_fuse_readl(hwpm, reg_offset, val) \
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tegra_hwpm_fuse_readl_impl(hwpm, reg_offset, val)
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#define tegra_hwpm_fuse_readl_prod_mode(hwpm, val) \
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tegra_hwpm_fuse_readl_prod_mode_impl(hwpm, val)
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#endif /* TEGRA_HWPM_SOC_H */
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