mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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cdbd6e7a24
This patch fixes issues found during testing
and guidance provided by devtools. The following
is changed in this patch:
1. mcf_iobhx and mcf_ocu are merged into a single mcf_soc IP.
2a. c2c is changed from 2 instances to 1.
2b. Remove C2CS0/1 which are the broadcast apertures.
Also remove the allowlist offset specific to broadcast
aperture.
3. mss_hub is changed from 1 instance to 8.
4. mss_channel is changed from 1 instance to 32.
5. mc0 perfmux is added to mcf_clink.
6. mcf_core is changed from 1 instance to 8.
7. License headers updated where necessary.
8. c2c allowlist updated to have just the offsets common
to all links.
9. Added a verbose comment explaining the design of
th500_hwpm_force_enable_ips()
10. Added back validate_current_config module parameter
as many systems still don't support fuses.
11. If all F's are read back for a regop in ip_readl(),
return -ENODEV.
There is a corresponding patch to update the python scripts
that generated many of the C and header files.
Bug 4287384
Change-Id: I8e14b0165dfa1abb9f5e04de577a41f0eb278246
Signed-off-by: Vishal Aslot <vaslot@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/3134365
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Eric Lu <ericlu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
85 lines
3.8 KiB
C
85 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/* SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef TH500_HWPM_INTERNAL_H
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#define TH500_HWPM_INTERNAL_H
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#include <hal/th500/soc/ip/mss_channel/th500_mss_channel.h>
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#include <hal/th500/soc/ip/rtr/th500_rtr.h>
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#include <hal/th500/soc/ip/pma/th500_pma.h>
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#include <hal/th500/soc/ip/c2c/th500_c2c.h>
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#include <hal/th500/soc/ip/smmu/th500_smmu.h>
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#include <hal/th500/soc/ip/cl2/th500_cl2.h>
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#include <hal/th500/soc/ip/c_nvlink/th500_nvlrx.h>
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#include <hal/th500/soc/ip/c_nvlink/th500_nvltx.h>
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#include <hal/th500/soc/ip/c_nvlink/th500_nvlctrl.h>
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#include <hal/th500/soc/ip/mss_hub/th500_mss_hub.h>
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#include <hal/th500/soc/ip/mcf_soc/th500_mcf_soc.h>
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#include <hal/th500/soc/ip/mcf_c2c/th500_mcf_c2c.h>
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#include <hal/th500/soc/ip/mcf_clink/th500_mcf_clink.h>
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#include <hal/th500/soc/ip/mcf_core/th500_mcf_core.h>
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#include <hal/th500/soc/ip/pcie/th500_pcie_xtlq.h>
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#include <hal/th500/soc/ip/pcie/th500_pcie_xtlrc.h>
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#include <hal/th500/soc/ip/pcie/th500_pcie_xalrc.h>
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#define TH500_HWPM_ACTIVE_IP_MAX TH500_HWPM_IP_MAX
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#define TH500_ACTIVE_IPS \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_RTR) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PMA) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_CHANNEL) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_C2C) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_C2C) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_SMMU) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_CL2) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLCTRL) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLRX) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_NVLTX) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MSS_HUB) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_SOC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CLINK) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MCF_CORE) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLQ) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XTLRC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_PCIE_XALRC) \
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DEFINE_SOC_HWPM_ACTIVE_IP(TH500_HWPM_ACTIVE_IP_MAX)
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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#define DEFINE_SOC_HWPM_ACTIVE_IP(name) name
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enum th500_hwpm_active_ips {
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TH500_ACTIVE_IPS
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};
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#undef DEFINE_SOC_HWPM_ACTIVE_IP
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struct tegra_soc_hwpm;
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bool th500_hwpm_validate_secondary_hals(struct tegra_soc_hwpm *hwpm);
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bool th500_hwpm_is_ip_active(struct tegra_soc_hwpm *hwpm,
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u32 ip_index, u32 *config_ip_index);
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bool th500_hwpm_is_resource_active(struct tegra_soc_hwpm *hwpm,
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u32 res_index, u32 *config_ip_index);
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u32 th500_get_rtr_int_idx(void);
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u32 th500_get_ip_max_idx(void);
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#endif /* TH500_HWPM_INTERNAL_H */
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