mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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e115e1da2f
HWPM components (PMA, RTR, perfmon) have MMIO address space and a corresponding virtual address region. It is possible that both MMIO and virtual addresses are same for an aperture. MMIO address of an aperture is used in device node to enable the aperture and further to map HWPM component in the driver. Virtual addresses are used by the applications to execute regops on HWPM apertures. Virtual addresses are also used to fake aperture address space in simulation. This patch updates - HWPM aperture structures to include MMIO address. - aperture ioremap function to use MMIO address values. - fake register allocation to use virtual address values. Jira THWPM-41 Change-Id: I05acb68dcb278722cd333e1187b2355d1d739e93 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> (cherry picked from commit 1c0e8107b4cddad7532c10dddc22bb30cef2540b) Reviewed-on: https://git-master.nvidia.com/r/c/linux-hwpm/+/2853213 Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
349 lines
9.1 KiB
C
349 lines
9.1 KiB
C
/*
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* Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/io.h>
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#include <uapi/linux/tegra-soc-hwpm-uapi.h>
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#include <tegra_hwpm.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_static_analysis.h>
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int tegra_hwpm_read_sticky_bits_impl(struct tegra_soc_hwpm *hwpm,
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u64 reg_base, u64 reg_offset, u32 *val)
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{
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void __iomem *ptr = NULL;
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u64 reg_addr = tegra_hwpm_safe_add_u64(reg_base, reg_offset);
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ptr = ioremap(reg_addr, 0x4);
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if (!ptr) {
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tegra_hwpm_err(hwpm, "Failed to map register(0x%llx)",
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reg_addr);
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return -ENODEV;
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}
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*val = __raw_readl(ptr);
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iounmap(ptr);
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return 0;
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}
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static int fake_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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if (!hwpm->fake_registers_enabled) {
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tegra_hwpm_err(hwpm, "Fake registers are disabled!");
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return -ENODEV;
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}
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*val = aperture->fake_registers[offset];
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return 0;
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}
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static int fake_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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if (!hwpm->fake_registers_enabled) {
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tegra_hwpm_err(hwpm, "Fake registers are disabled!");
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return -ENODEV;
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}
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aperture->fake_registers[offset] = val;
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return 0;
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}
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/*
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* Read IP domain registers
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* IP(except PMA and RTR) perfmux fall in this category
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*/
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static int ip_readl(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset);
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if (hwpm->fake_registers_enabled) {
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return fake_readl(hwpm, aperture, offset, val);
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} else {
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struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
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if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
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int err = 0;
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err = (*ip_ops_ptr->hwpm_ip_reg_op)(ip_ops_ptr->ip_dev,
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TEGRA_SOC_HWPM_IP_REG_OP_READ,
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aperture->element_index, offset, val);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "Aperture (0x%llx-0x%llx) "
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"read offset(0x%llx) failed",
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aperture->start_abs_pa,
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aperture->end_abs_pa, offset);
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return err;
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}
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} else {
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/* Fall back to un-registered IP method */
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void __iomem *ptr = NULL;
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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aperture->start_pa, offset);
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ptr = ioremap(reg_addr, 0x4);
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if (!ptr) {
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tegra_hwpm_err(hwpm,
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"Failed to map register(0x%llx)",
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reg_addr);
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return -ENODEV;
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}
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*val = __raw_readl(ptr);
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iounmap(ptr);
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}
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}
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return 0;
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}
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/*
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* Write to IP domain registers
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* IP(except PMA and RTR) perfmux fall in this category
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*/
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static int ip_writel(struct tegra_soc_hwpm *hwpm, struct hwpm_ip_inst *ip_inst,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx) val(0x%x)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
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if (hwpm->fake_registers_enabled) {
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return fake_writel(hwpm, aperture, offset, val);
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} else {
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struct tegra_hwpm_ip_ops *ip_ops_ptr = &ip_inst->ip_ops;
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if (ip_ops_ptr->hwpm_ip_reg_op != NULL) {
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int err = 0;
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err = (*ip_ops_ptr->hwpm_ip_reg_op)(ip_ops_ptr->ip_dev,
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TEGRA_SOC_HWPM_IP_REG_OP_WRITE,
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aperture->element_index, offset, &val);
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if (err < 0) {
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tegra_hwpm_err(hwpm, "Aperture (0x%llx-0x%llx) "
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"write offset(0x%llx) val 0x%x failed",
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aperture->start_abs_pa,
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aperture->end_abs_pa, offset, val);
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return err;
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}
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} else {
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/* Fall back to un-registered IP method */
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void __iomem *ptr = NULL;
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u64 reg_addr = tegra_hwpm_safe_add_u64(
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aperture->start_pa, offset);
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ptr = ioremap(reg_addr, 0x4);
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if (!ptr) {
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tegra_hwpm_err(hwpm,
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"Failed to map register(0x%llx)",
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reg_addr);
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return -ENODEV;
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}
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__raw_writel(val, ptr);
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iounmap(ptr);
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}
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}
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return 0;
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}
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/*
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* Read HWPM domain registers
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* PERFMONs, PMA and RTR registers fall in this category
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*/
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static int hwpm_readl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 *val)
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{
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset);
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if (hwpm->fake_registers_enabled) {
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return fake_readl(hwpm, aperture, offset, val);
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} else {
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if (aperture->dt_mmio == NULL) {
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tegra_hwpm_err(hwpm,
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"aperture is not iomapped as expected");
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return -ENODEV;
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}
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*val = readl(aperture->dt_mmio + offset);
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}
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return 0;
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}
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/*
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* Write to HWPM domain registers
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* PERFMONs, PMA and RTR registers fall in this category
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*/
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static int hwpm_writel(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 offset, u32 val)
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{
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int err = 0;
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tegra_hwpm_dbg(hwpm, hwpm_register,
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"Aperture (0x%llx-0x%llx) offset(0x%llx) val(0x%x)",
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aperture->start_abs_pa, aperture->end_abs_pa, offset, val);
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if (hwpm->fake_registers_enabled) {
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err = fake_writel(hwpm, aperture, offset, val);
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} else {
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if (aperture->dt_mmio == NULL) {
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tegra_hwpm_err(hwpm,
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"aperture is not iomapped as expected");
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return -ENODEV;
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}
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writel(val, aperture->dt_mmio + offset);
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}
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return err;
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}
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/*
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* Read a HWPM domain register. It is assumed that valid aperture
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* is passed to the function.
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*/
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int tegra_hwpm_readl_impl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 *val)
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{
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tegra_hwpm_fn(hwpm, " ");
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return -ENODEV;
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}
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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/*
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* Register address passed for perfmon access is with
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* respect to first perfmon block.
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* Hence, subtract base_addr from given addr for offset.
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*/
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u64 reg_offset = tegra_hwpm_safe_sub_u64(
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addr, aperture->base_pa);
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/* HWPM domain registers */
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return hwpm_readl(hwpm, aperture, reg_offset, val);
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} else {
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tegra_hwpm_err(hwpm, "IP aperture read is not expected");
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Write to a HWPM domain register. It is assumed that valid aperture
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* is passed to the function.
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*/
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int tegra_hwpm_writel_impl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *aperture, u64 addr, u32 val)
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{
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tegra_hwpm_fn(hwpm, " ");
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return -ENODEV;
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}
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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/*
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* Register address passed for perfmon access is with
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* respect to first perfmon block.
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* Hence, subtract base_addr from given addr for offset.
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*/
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u64 reg_offset = tegra_hwpm_safe_sub_u64(
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addr, aperture->base_pa);
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/* HWPM domain internal registers */
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return hwpm_writel(hwpm, aperture, reg_offset, val);
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} else {
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tegra_hwpm_err(hwpm, "IP aperture write is not expected");
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Read a register from the EXEC_REG_OPS IOCTL. It is assumed that the allowlist
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* check has been done before calling this function.
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*/
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int tegra_hwpm_regops_readl_impl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
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u64 addr, u32 *val)
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{
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u64 reg_offset = 0ULL;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return -ENODEV;
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}
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/*
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* Register address passed to this function always belong to
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* virtual address range of the aperture.
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* Hence, subtract start_abs_pa from given addr for offset.
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*/
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reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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err = hwpm_readl(hwpm, aperture, reg_offset, val);
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} else {
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err = ip_readl(hwpm, ip_inst, aperture, reg_offset, val);
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}
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return err;
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}
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/*
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* Write a register from the EXEC_REG_OPS IOCTL. It is assumed that the
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* allowlist check has been done before calling this function.
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*/
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int tegra_hwpm_regops_writel_impl(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_inst *ip_inst, struct hwpm_ip_aperture *aperture,
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u64 addr, u32 val)
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{
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u64 reg_offset = 0ULL;
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int err = 0;
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tegra_hwpm_fn(hwpm, " ");
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if (!aperture) {
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tegra_hwpm_err(hwpm, "aperture is NULL");
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return -ENODEV;
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}
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/*
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* Register address passed to this function always belong to
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* virtual address range of the aperture.
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* Hence, subtract start_abs_pa from given addr for offset.
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*/
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reg_offset = tegra_hwpm_safe_sub_u64(addr, aperture->start_abs_pa);
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if ((aperture->element_type == HWPM_ELEMENT_PERFMON) ||
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(aperture->element_type == HWPM_ELEMENT_PERFMUX)) {
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err = hwpm_writel(hwpm, aperture, reg_offset, val);
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} else {
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err = ip_writel(hwpm, ip_inst, aperture, reg_offset, val);
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}
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return err;
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}
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