mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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ea5e4e406b
Add below HALs to make code chip agnostic. This will allow us to use t234 specific HALs for next chips. - get_pma_int_idx: get PMA's internal index corresponding to active chip - get_rtr_int_idx: get RTR's internal index corresponding to active chip - get_ip_max_idx: get MAX IP index corresponding to active chip Move chip agnostic code to common files. Jira THWPM-41 Change-Id: I5518469b1473fe7f66b6517cee729cf46520bbac Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2675515 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
76 lines
3.1 KiB
C
76 lines
3.1 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef TEGRA_HWPM_COMMON_H
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#define TEGRA_HWPM_COMMON_H
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struct tegra_soc_hwpm;
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struct tegra_soc_hwpm_exec_reg_ops;
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struct tegra_soc_hwpm_ip_floorsweep_info;
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struct tegra_soc_hwpm_alloc_pma_stream;
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struct tegra_soc_hwpm_update_get_put;
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struct tegra_soc_hwpm_ip_ops;
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struct hwpm_ip_aperture;
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typedef struct hwpm_ip_aperture hwpm_ip_perfmon;
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typedef struct hwpm_ip_aperture hwpm_ip_perfmux;
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int tegra_hwpm_init_sw_components(struct tegra_soc_hwpm *hwpm);
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void tegra_hwpm_release_sw_components(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_reserve_resource(struct tegra_soc_hwpm *hwpm, u32 resource);
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int tegra_hwpm_release_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_bind_resources(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_reserve_pma(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_reserve_rtr(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_release_pma(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_release_rtr(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_perfmon_reserve(struct tegra_soc_hwpm *hwpm,
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hwpm_ip_perfmon *perfmon);
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int tegra_hwpm_perfmon_release(struct tegra_soc_hwpm *hwpm,
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hwpm_ip_perfmon *perfmon);
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int tegra_hwpm_perfmux_reserve(struct tegra_soc_hwpm *hwpm,
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hwpm_ip_perfmux *perfmux);
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int tegra_hwpm_perfmux_release(struct tegra_soc_hwpm *hwpm,
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hwpm_ip_perfmux *perfmux);
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int tegra_hwpm_init_chip_ip_structures(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_set_fs_info_ip_ops(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops,
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u64 base_address, u32 ip_idx, bool available);
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int tegra_hwpm_finalize_chip_info(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_get_allowlist_size(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_update_allowlist(struct tegra_soc_hwpm *hwpm,
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void *ioctl_struct);
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int tegra_hwpm_exec_regops(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_exec_reg_ops *exec_reg_ops);
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int tegra_hwpm_setup_hw(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_setup_sw(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_disable_triggers(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_release_hw(struct tegra_soc_hwpm *hwpm);
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void tegra_hwpm_release_sw_setup(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_ip_floorsweep_info *fs_info);
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int tegra_hwpm_map_stream_buffer(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_alloc_pma_stream *alloc_pma_stream);
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int tegra_hwpm_clear_mem_pipeline(struct tegra_soc_hwpm *hwpm);
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int tegra_hwpm_update_mem_bytes(struct tegra_soc_hwpm *hwpm,
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struct tegra_soc_hwpm_update_get_put *update_get_put);
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#endif /* TEGRA_HWPM_COMMON_H */
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