mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
synced 2025-12-24 10:13:00 +03:00
92be6f7a00
- Update HWPM driver to add HAL layer. This will allow support for multiple chips. - Add below data structure hierarchy for HWPM driver HWPM driver structure -> chip info struct -> ip info array -> perfmux/perfmon info array NOTE: To make commit message more legible, using "aperture" instead of "perfmux and/or perfmon" - Chip info structure contains - Array of IP info - HAL function pointers - IP info structure contains IP specific info - Number of instances - Number of apertures per instance - Aperture ranges, strides, static info array - Aperture dynamic arrays - Aperture info structure contains - Hw index - Physical address info - MMIO address info - Add separate IP info files - Create separate files that include logic for allowlist, memory buffer, resources, ip, regops to make functions more legible. - Move probe, ioctl and io functions to os/linux path. - Add fn, info, register and verbose debug log levels to controls debug messages - add debugfs node to update dbg_mask - Correct MGBE perfmux base address Jira THWPM-41 Change-Id: I8ffdaa657789e2a187cbb98502d0359bb57f9c54 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2651377 Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit
119 lines
3.2 KiB
C
119 lines
3.2 KiB
C
/*
|
|
* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*/
|
|
|
|
#include <soc/tegra/fuse.h>
|
|
#include <uapi/linux/tegra-soc-hwpm-uapi.h>
|
|
|
|
#include <tegra_hwpm_log.h>
|
|
#include <tegra_hwpm_io.h>
|
|
#include <tegra_hwpm.h>
|
|
|
|
struct platform_device *tegra_soc_hwpm_pdev;
|
|
|
|
#define REGISTER_IP true
|
|
#define UNREGISTER_IP false
|
|
|
|
void tegra_soc_hwpm_ip_register(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
|
|
{
|
|
struct tegra_soc_hwpm *hwpm = NULL;
|
|
int ret = 0;
|
|
|
|
if (tegra_soc_hwpm_pdev == NULL) {
|
|
tegra_hwpm_dbg(hwpm, hwpm_info,
|
|
"IP %d trying to register. HWPM device not available",
|
|
hwpm_ip_ops->ip_index);
|
|
} else {
|
|
if (hwpm_ip_ops->ip_dev == NULL) {
|
|
tegra_hwpm_err(hwpm, "IP dev to register is NULL");
|
|
return;
|
|
}
|
|
hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_info,
|
|
"Register IP 0x%llx", hwpm_ip_ops->ip_base_address);
|
|
|
|
if (hwpm->active_chip->extract_ip_ops == NULL) {
|
|
tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized");
|
|
return;
|
|
}
|
|
ret = hwpm->active_chip->extract_ip_ops(hwpm,
|
|
hwpm_ip_ops, REGISTER_IP);
|
|
if (ret < 0) {
|
|
tegra_hwpm_err(hwpm, "Failed to set IP ops for IP %d",
|
|
hwpm_ip_ops->ip_index);
|
|
}
|
|
}
|
|
}
|
|
|
|
void tegra_soc_hwpm_ip_unregister(struct tegra_soc_hwpm_ip_ops *hwpm_ip_ops)
|
|
{
|
|
struct tegra_soc_hwpm *hwpm = NULL;
|
|
int ret = 0;
|
|
|
|
if (tegra_soc_hwpm_pdev == NULL) {
|
|
tegra_hwpm_dbg(hwpm, hwpm_info, "HWPM device not available");
|
|
} else {
|
|
if (hwpm_ip_ops->ip_dev == NULL) {
|
|
tegra_hwpm_err(hwpm, "IP dev to unregister is NULL");
|
|
return;
|
|
}
|
|
hwpm = platform_get_drvdata(tegra_soc_hwpm_pdev);
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_info,
|
|
"Unregister IP 0x%llx", hwpm_ip_ops->ip_base_address);
|
|
|
|
if (hwpm->active_chip->extract_ip_ops == NULL) {
|
|
tegra_hwpm_err(hwpm, "extract_ip_ops uninitialized");
|
|
return;
|
|
}
|
|
ret = hwpm->active_chip->extract_ip_ops(hwpm,
|
|
hwpm_ip_ops, UNREGISTER_IP);
|
|
if (ret < 0) {
|
|
tegra_hwpm_err(hwpm, "Failed to reset IP ops for IP %d",
|
|
hwpm_ip_ops->ip_index);
|
|
}
|
|
}
|
|
}
|
|
|
|
int tegra_soc_hwpm_get_floorsweep_info(struct tegra_soc_hwpm *hwpm,
|
|
struct tegra_soc_hwpm_ip_floorsweep_info *fs_info)
|
|
{
|
|
int ret = 0;
|
|
u32 i = 0U;
|
|
|
|
tegra_hwpm_fn(hwpm, " ");
|
|
|
|
if (hwpm->active_chip->get_fs_info == NULL) {
|
|
tegra_hwpm_err(hwpm, "get_fs_info uninitialized");
|
|
return -ENODEV;
|
|
}
|
|
|
|
for (i = 0U; i < fs_info->num_queries; i++) {
|
|
ret = hwpm->active_chip->get_fs_info(
|
|
hwpm, (u32)fs_info->ip_fsinfo[i].ip_type,
|
|
&fs_info->ip_fsinfo[i].ip_inst_mask,
|
|
&fs_info->ip_fsinfo[i].status);
|
|
if (ret < 0) {
|
|
/* Print error for debug purpose. */
|
|
tegra_hwpm_err(hwpm, "Failed to get fs_info");
|
|
}
|
|
|
|
tegra_hwpm_dbg(hwpm, hwpm_verbose,
|
|
"Query %d: ip_type %d: ip_status: %d inst_mask 0x%llx",
|
|
i, fs_info->ip_fsinfo[i].ip_type,
|
|
fs_info->ip_fsinfo[i].status,
|
|
fs_info->ip_fsinfo[i].ip_inst_mask);
|
|
}
|
|
return ret;
|
|
}
|