mirror of
git://nv-tegra.nvidia.com/linux-hwpm.git
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f91708325e
Allowlist, get IP/resource info and perfmux disable HALs defined in t234 specific files do not require any chip specific details. Move such functions to common files. This way common functions can be reused by future chips, reducing maintainability of these functions. Rename linux specific get_resource_info and get_floorsweep_info functions to avoid multiple definitions. Jira THPM-41 Change-Id: I0fc9eaf5b5d2591fa740939e1a43fe6911b5a378 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2780702 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <tegra_hwpm_log.h>
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#include <tegra_hwpm_io.h>
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#include <tegra_hwpm.h>
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#include <hal/t234/t234_internal.h>
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#include <hal/t234/hw/t234_pmasys_soc_hwpm.h>
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#include <hal/t234/hw/t234_pmmsys_soc_hwpm.h>
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int t234_hwpm_perfmon_enable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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/* Enable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_bind,
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"Enabling PERFMON(0x%llx - 0x%llx)",
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perfmon->start_abs_pa, perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_sys0_enginestatus_enable_m(),
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pmmsys_sys0_enginestatus_enable_out_f());
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err = tegra_hwpm_writel(hwpm, perfmon,
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pmmsys_sys0_enginestatus_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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int t234_hwpm_perfmon_disable(struct tegra_soc_hwpm *hwpm,
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struct hwpm_ip_aperture *perfmon)
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{
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int err = 0;
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u32 reg_val;
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tegra_hwpm_fn(hwpm, " ");
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if (perfmon->element_type == HWPM_ELEMENT_PERFMUX) {
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/*
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* Since HWPM elements use perfmon functions,
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* skip disabling HWPM PERFMUX elements
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*/
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return 0;
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}
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/* Disable */
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tegra_hwpm_dbg(hwpm, hwpm_dbg_release_resource,
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"Disabling PERFMON(0x%llx - 0x%llx)",
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perfmon->start_abs_pa, perfmon->end_abs_pa);
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err = tegra_hwpm_readl(hwpm, perfmon, pmmsys_control_r(0), ®_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm read failed");
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return err;
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}
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reg_val = set_field(reg_val, pmmsys_control_mode_m(),
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pmmsys_control_mode_disable_f());
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err = tegra_hwpm_writel(hwpm, perfmon, pmmsys_control_r(0), reg_val);
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if (err != 0) {
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tegra_hwpm_err(hwpm, "hwpm write failed");
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return err;
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}
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return 0;
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}
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