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Enum tegra_soc_hwpm_ip is defined to query IP information. To untangle its use from HWPM related functionality, enum tegra_soc_hwpm_resource should be used by IP drivers to register with HWPM. An IP can have multiple instances with multiple IP core elements in each instance. Currently, the IP <-> HWPM register access API passes register offset only. However, it is not possible to figure out requested specific register access only with register offset. For example, MC device has one instance with 16 duplicate channels. To access channel x perfmux register, HWPM driver should pass perfmux register offset alongwith channel number (index). Add instance element index as an argument to the register access API, tegra_soc_hwpm_ip_ops.hwpm_ip_reg_op(). -Update internal copy of tegra_soc_hwpm_ip_ops. -Update hwpm_ip_reg_op() implemented in flcn driver. -Update hwpm_ip_reg_op() implemented in pva driver. Update hwpm_ip_pm() in flcn driver to use nvhost power management APIs. Bug 3573882 Jira THWPM-8 Change-Id: I0138927f383e9a67085816132ce33538bd609560 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2713274 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Vasuki Shankar <vasukis@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Seema Khowala <seemaj@nvidia.com> GVS: Gerrit_Virtual_Submit