/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 */

#define HOST1X_COMMON_OFA_MLOCK			0x4050
#define HOST1X_COMMON_NVJPG1_MLOCK		0x4070
#define HOST1X_COMMON_VIC_MLOCK			0x4078
#define HOST1X_COMMON_NVENC_MLOCK		0x407c
#define HOST1X_COMMON_NVDEC_MLOCK		0x4080
#define HOST1X_COMMON_NVJPG_MLOCK		0x4084

#define HOST1X_COMMON_INTR_CPU0_MASK		0x4
#define HOST1X_COMMON_THOST_INTRSTATUS		0x1c
#define HOST1X_COMMON_THOST_INTRMASK		0x30
#define HOST1X_COMMON_THOST_GLOBAL_INTRMASK	0x44

#define HOST1X_COMMON_THOST_INTRMASK_NVENC_ACTMON(v)		(v << 2)
#define HOST1X_COMMON_THOST_INTRMASK_VIC_ACTMON(v)		(v << 3)
#define HOST1X_COMMON_THOST_INTRMASK_NVDEC_ACTMON(v)		(v << 4)
#define HOST1X_COMMON_THOST_INTRMASK_NVJPG_ACTMON(v)		(v << 5)
#define HOST1X_COMMON_THOST_INTRMASK_NVJPG1_ACTMON(v)		(v << 6)
#define HOST1X_COMMON_THOST_INTRMASK_OFA_ACTMON(v)		(v << 7)

#define HOST1X_COMMON_THOST_INTRSTATUS_NVENC_ACTMON_INTR	BIT(2)
#define HOST1X_COMMON_THOST_INTRSTATUS_VIC_ACTMON_INTR		BIT(3)
#define HOST1X_COMMON_THOST_INTRSTATUS_NVDEC_ACTMON_INTR	BIT(4)
#define HOST1X_COMMON_THOST_INTRSTATUS_NVJPG_ACTMON_INTR	BIT(5)
#define HOST1X_COMMON_THOST_INTRSTATUS_NVJPG1_ACTMON_INTR	BIT(6)
#define HOST1X_COMMON_THOST_INTRSTATUS_OFA_ACTMON_INTR		BIT(7)
