# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-tegra234.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra234 pin controller

maintainers:
  - Laxman Dewangan <ldewangan@nvidia.com>
  - Prathamesh Shete <pshete@nvidia.com>

description:
  Bindings for NVIDIA Tegra234 pin controller

properties:
  compatible:
    enum:
      - nvidia,tegra234-pinmux

  reg:
    items:
      - description: Base address and size of the GPIO controller.
      - description: Base address and size of the pinmux controller.

  '#gpio-range-cells':
    const: 3
    description:
      GPIO range cells size of the pins.

required:
  - compatible
  - reg

patternProperties:
  '^.*$':
    patternProperties:
      '^.*$':
        type: object
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured either in display or i2c mode.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          nvidia,pins:
            $ref: "/schemas/types.yaml#/definitions/string"
            description:
              Name of the pins.
            enum: [ touch_clk_pcc4, uart3_rx_pcc6, uart3_tx_pcc5, gen8_i2c_sda_pdd2, gen8_i2c_scl_pdd1,
                    spi2_mosi_pcc2, gen2_i2c_scl_pcc7, spi2_cs0_pcc3, gen2_i2c_sda_pdd0, spi2_sck_pcc0,
                    spi2_miso_pcc1, can1_dout_paa2, can1_din_paa3, can0_dout_paa0, can0_din_paa1 can0_stb_paa4,
                    can0_en_paa5, soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0, can1_en_pbb1, soc_gpio50_pbb2,
                    can1_err_pbb3, soc_gpio08_pb0, soc_gpio36_pm5, soc_gpio53_pm6, soc_gpio55_pm4, soc_gpio38_pm7,
                    soc_gpio39_pn1, soc_gpio40_pn2, dp_aux_ch0_hpd_pm0, dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
                    dp_aux_ch3_hpd_pm3, dp_aux_ch1_p_pn3, dp_aux_ch1_n_pn4, dp_aux_ch2_p_pn5, dp_aux_ch2_n_pn6,
                    dp_aux_ch3_p_pn7, dp_aux_ch3_n_pn0, eqos_td3_pe4, eqos_td2_pe3, eqos_td1_pe2, eqos_td0_pe1,
                    eqos_rd3_pf1, eqos_rd2_pf0, eqos_rd1_pe7, eqos_sma_mdio_pf4, eqos_rd0_pe6, eqos_sma_mdc_pf5,
                    eqos_comp, eqos_txc_pe0, eqos_rxc_pf3, eqos_tx_ctl_pe5, eqos_rx_ctl_pf2, pex_l2_clkreq_n_pk4,
                    pex_wake_n_pl2, pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3, pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
                    pex_l2_rst_n_pk5, pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7, pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
                    soc_gpio34_pl3, pex_l5_clkreq_n_paf0, pex_l5_rst_n_paf1, pex_l6_clkreq_n_paf2,  PE6,
                    pex_l6_rst_n_paf3, pex_l10_clkreq_n_pag6, pex_l10_rst_n_pag7, pex_l7_clkreq_n_pag0,
                    pex_l7_rst_n_pag1, pex_l8_clkreq_n_pag2, pex_l8_rst_n_pag3, pex_l9_clkreq_n_pag4,
                    pex_l9_rst_n_pag5, qspi0_io3_pc5, qspi0_io2_pc4, qspi0_io1_pc3, qspi0_io0_pc2,
                    qspi0_sck_pc0, qspi0_cs_n_pc1, qspi1_io3_pd3, qspi1_io2_pd2, qspi1_io1_pd1, qspi1_io0_pd0,
                    qspi1_sck_pc6, qspi1_cs_n_pc7, qspi_comp, sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_comp,
                    sdmmc1_dat3_pj5, sdmmc1_dat2_pj4, sdmmc1_dat1_pj3, sdmmc1_dat0_pj2, sce_error_pee0,
                    batt_oc_pee3, bootv_ctl_n_pee7, power_on_pee4, soc_gpio26_pee5, soc_gpio27_pee6,
                    ao_retention_n_pee2, vcomp_alert_pee1, hdmi_cec_pgg0, ufs0_rst_n_pae1, ufs0_ref_clk_pae0,
                    spi3_miso_py1, spi1_cs0_pz6, spi3_cs0_py3, spi1_miso_pz4, spi3_cs1_py4, spi1_sck_pz3,
                    spi3_sck_py0, spi1_cs1_pz7, spi1_mosi_pz5, spi3_mosi_py2, uart2_tx_px4, uart2_rx_px5,
                    uart2_rts_px6, uart2_cts_px7, uart5_tx_py5, uart5_rx_py6, uart5_rts_py7, uart5_cts_pz0,
                    gpu_pwr_req_px0, gp_pwm3_px3, gp_pwm2_px2, cv_pwr_req_px1, usb_vbus_en0_pz1, usb_vbus_en1_pz2,
                    extperiph2_clk_pp1, extperiph1_clk_pp0, cam_i2c_sda_pp3, cam_i2c_scl_pp2, soc_gpio23_pp4,
                    soc_gpio24_pp5, soc_gpio25_pp6, pwr_i2c_scl_pp7, pwr_i2c_sda_pq0, soc_gpio28_pq1, soc_gpio29_pq2,
                    soc_gpio30_pq3, soc_gpio31_pq4, soc_gpio32_pq5, soc_gpio33_pq6, soc_gpio35_pq7, soc_gpio37_pr0,
                    soc_gpio56_pr1, uart1_cts_pr5, uart1_rts_pr4, uart1_rx_pr3, uart1_tx_pr2, cpu_pwr_req_pi5,
                    uart4_cts_ph6, uart4_rts_ph5, uart4_rx_ph4, uart4_tx_ph3, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
                    soc_gpio20_pg7, soc_gpio21_ph0, soc_gpio22_ph1, soc_gpio13_pg0, soc_gpio14_pg1, soc_gpio15_pg2,
                    soc_gpio16_pg3, soc_gpio17_pg4, soc_gpio18_pg5, soc_gpio19_pg6, soc_gpio41_ph7, soc_gpio42_pi0,
                    soc_gpio43_pi1, soc_gpio44_pi2, soc_gpio06_ph2, soc_gpio07_pi6, dap4_sclk_pa4, dap4_dout_pa5,
                    dap4_din_pa6, dap4_fs_pa7, dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2, dap6_fs_pa3, soc_gpio45_pad0,
                    soc_gpio46_pad1, soc_gpio47_pad2, soc_gpio48_pad3, soc_gpio57_pac4, soc_gpio58_pac5, soc_gpio59_pac6,
                    soc_gpio60_pac7, spi5_cs0_pac3, spi5_miso_pac1, spi5_mosi_pac2, spi5_sck_pac0, ]

          nvidia,function:
            $ref: "/schemas/types.yaml#/definitions/string"
            description:
              Functions of the pins.
            enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, eth1, dp,
                    eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, pe4, pe5, pe6, pe10,
                    pe7, pe8, pe9, qspi0, qspi1, qspi, sdmmc1, sce, soc, gpio, hdmi, ufs0,
                    spi3, spi1, uartb, uarte, usb, extperiph2, extperiph1, i2c3, vi0, i2c5,
                    uarta, uartd, i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
                    dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, ccla, i2s2,
                    i2s1, i2s8, i2s3, rsvd2, dmic5, dca, displayb, displaya, vi1, dcb, dmic1,
                    dmic4, i2s7, dmic2, dspk0, rsvd3, tsc_alt, istctrl, vi1_alt, dspk1 ]

          nvidia,pull:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Representing the pull-down/up to apply to the pin.
              Valid values are  0  none, 1 down, 2 up.

          nvidia,tristate:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Tristate on pin to be enable or not. 0 drive, 1 tristate.

          nvidia,enable-input:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Enable the direction of pin as input. Else it is output only.
              Value of 1 will make the pin as input.

          nvidia,open-drain:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Enable the open drain behavior of pin. If open drain enabled then
              pin will not drive the high but make the high impedencae with pull-up
              for making the line high.
              Value of 1 is for enable and 0 for disable.

          nvidia,lock:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Lock the pin functionality and do not allow any chnage in the configuration.
              Only SoC reset will disable the lock.
              Value of 1 will enable the lock.

          nvidia,io-reset:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Enable the IO reset of pins. For making the signal active, the pin needs to
              bring out of state.
              Value of 1 will keep the pin in reset state.

          nvidia,rcv-sel:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
               Select VIL/VIH receivers.
               Value of 0 is normal and 1 is high.

          nvidia,io-hv:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Pin can work in dual voltage level. Select high-voltage receivers.
              Value of 0 means normal voltage and 1 means high voltage.

          nvidia,loopback:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Enable loopback of the signal in pins.
              Value of 1 means enable loop back and 0 means disable of the loopback.

          nvidia,high-speed-mode:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Configure the pin in high speed or normal speed.
              Value of 1 means enable the high speed and 0 menas disable the high speed.

          nvidia,schmitt:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Configure the pin in schemitt enable or not.
              Value of 1 means schimitt enable and 0 means schimitt disable.

          nvidia,low-power-mode:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Configure pin in low power mode when it is not used for IO power saving.
              Value of 1 means enable the pin in low power mode and 0 means disable the
              low power mode.

          nvidia,pull-down-strength:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Configure the pull down strength of the pin if it is configure in pull down mode.
              0 is weakest.
              The range of valid values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM.

          nvidia,pull-up-strength:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
               Controls drive strength. 0 is weakest.
               The range of valid values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM.

          nvidia,slew-rate-falling:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
               Controls falling signal slew rate. 0 is fastest. The range of valid values depends
               on the pingroup. See "DRVUP_SLWF" in the Tegra TRM.

          nvidia,slew-rate-rising:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
              Controls rising signal slew rate. 0 is fastest. The range of valid values depends
              on the pingroup. See "DRVDN_SLWR" in the Tegra TRM.

          nvidia,drive-type:
            $ref: "/schemas/types.yaml#/definitions/uint32"
            description:
               Drive type of the pin. Valid range 0...3.

        required:
          - nvidia,pins

additionalProperties: false

examples:
  - |
    #define TEGRA_PIN_PULL_NONE 0
    #define TEGRA_PIN_DISABLE   0
    #define TEGRA_PIN_ENABLE    1
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pinmux@2430000 {
           compatible = "nvidia,tegra234-pinmux";
           reg = <0x0 0x2430000 0x0 0x19100>,
                 <0x0 0xc300000 0x0 0x4000>;
           #gpio-range-cells = <3>;

           pinmux_default: common {
              /* SFIO Pin Configuration */

               ao_retention_n_pee2 {
                  nvidia,pins = "ao_retention_n_pee2";
                  nvidia,function = "istctrl";
                  nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                  nvidia,tristate = <TEGRA_PIN_DISABLE>;
                  nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                  nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                  nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };

                hdmi_cec_pgg0 {
                  nvidia,pins = "hdmi_cec_pgg0";
                  nvidia,function = "hdmi";
                  nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                  nvidia,tristate = <TEGRA_PIN_ENABLE>;
                  nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                  nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                  nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                };

            };
         };
     };
...
