# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-tegra194-pexclk-padctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra PEX pad controller.

maintainers:
  - Laxman Dewangan <ldewangan@nvidia.com>

description:
  Bindings for NVIDIA Tegra PEX pad controller.

properties:
  compatible:
    const: nvidia,tegra194-pexclk-padctl

  reg:
    items:
      - description: Base address and size of the MISC controller.
      - description: Base address and size of the PMC controller.

required:
  - compatible
  - reg


patternProperties:
  'pinmux-[0-9]*$':
    type: object
    patternProperties:
      '-pins*$':
        type: object
        description: |
          A pinctrl node should contain at least one subnodes representing the
          pinctrl groups available on the machine. Each subnode will list the
          pins it needs, and how they should be configured either in display or i2c mode.
        $ref: "/schemas/pinctrl/pincfg-node.yaml"

        properties:
          nvidia,pexclk-single-en:
            $ref: /schemas/types.yaml#/definitions/uint32
            description:
              Enable/disable the pex clock in the pad or not. 1 for enable and 0 for disable.
          pins:
            enum: [ pexclk ]
            description:
              Name of pins.

additionalProperties: false

examples:
  - |
    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pinctrl@3790000 {
           compatible = "nvidia,tegra194-pexclk-padctl";
           reg = <0x0 0x03790000 0x0 0x1000>,
                 <0x0 0x037a0000 0x0 0x1000>;

           pexclk_default: pinmux-0 {
              pexclk-pins {
                  pins = "pexclk";
                  nvidia,pexclk-single-en = <1>;
              };
           };
        };
     };
...
