/* SPDX-License-Identifier: GPL-2.0-only */
/* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */

#ifndef PVA_CONSTANTS_H
#define PVA_CONSTANTS_H

#define PVA_NUM_ENGINES 2U
#define PVA_MAX_NUM_CCQ 8
#define PVA_CCQ_DEPTH 14U
#define PVA_USER_CCQ_BASE 1
#define PVA_INVALID_CCQ_ID 0xFF
#define PVA_INVALID_ENGINE_ID 0xFFU

/* CCQ status 6 is used to store checkpoint value */
#define PVA_REG_CCQ_STATUS6_IDX 6
#define PVA_CFG_CCQ_STATUS_COUNT 9
#define PVA_CFG_CCQ_BLOCK_SIZE 0x10000

// Max of T26X and T23X
#define PVA_MAX_NUM_SMMU_CONTEXTS 10

#define PVA_NUM_SMMU_CONTEXTS_T23X 9
#define PVA_NUM_SMMU_CONTEXTS_T26X 10

#define PVA_MAX_NUM_USER_CONTEXTS 7u

#define PVA_R5_SMMU_CONTEXT_ID 0

#define TIME_MS_TO_NS 1000000U
#define TIME_MS_TO_US 1000U
#define TIME_US_TO_NS 1000U
#define TIME_US_TO_MS 1000U

#define PVA_PRIV_CCQ_ID 0
#define PVA_INVALID_QUEUE_ID 0xFF

#define PVA_MAX_NUM_CHUNKS_PER_CONTEXT 128
#define PVA_MAX_NUM_SUBMIT 256

#define PVA_MAX_NUM_PVAS 1
#define PVA_NUM_PVE 2

#define PVA_MAX_NUM_RESETS 1
#define PVA_MAX_NUM_CLOCKS 3

#define PVA_MAX_NUM_QUEUES_PER_CONTEXT 8u
#define PVA_NUM_RW_SYNCPTS_PER_CONTEXT PVA_MAX_NUM_QUEUES_PER_CONTEXT

#define PVA_MAX_NUM_DMA_CONFIGS_PER_CONTEXT 1024

#define PVA_MAX_NUM_SEMAPHORES 1024

#define MAX_BYTES_PER_PIXEL 0x3U

#define PVA_NUM_DMA_TRIGGERS 9

#define PVA_NUM_RESERVED_CHANNELS (1U)

#define PVA_RESERVED_DMA_CHANNEL 0U

#define PVA_NUM_RESERVED_DESCRIPTORS (4U)

#define PVA_RESERVED_DESCRIPTORS_START 60U

#define PVA_RESERVED_DESCRIPTORS_END                                           \
	((PVA_RESERVED_DESCRIPTORS_START) + (PVA_NUM_RESERVED_DESCRIPTORS)-1U)

//T26X defines
#define PVA_NUM_HWSEQ_WORDS_T26X (512U)

#define PVA_NUM_DMA_DESC_T26X (96U)

#define PVA_DMA_NUM_CHANNELS_T26X (16U)

#define PVA_NUM_DMA_ADB_BUFFS_T26X (304U)

#define PVA_NUM_RESERVED_ADB_BUFFERS_T26X (16U)

#define PVA_NUM_DYNAMIC_ADB_BUFFS_T26X                                         \
	(PVA_NUM_DMA_ADB_BUFFS_T26X - PVA_NUM_RESERVED_ADB_BUFFERS_T26X)

#define PVA_NUM_VMEM_REGIONS_T26X (4U)
//T23X defines
#define PVA_NUM_HWSEQ_WORDS_T23X 256U

#define PVA_NUM_DMA_DESC_T23X (64U)

#define PVA_DMA_NUM_CHANNELS_T23X (16U)

#define PVA_NUM_DMA_ADB_BUFFS_T23X (272U)

#define PVA_NUM_RESERVED_ADB_BUFFERS_T23X (16U)

#define PVA_NUM_DYNAMIC_ADB_BUFFS_T23X                                         \
	(PVA_NUM_DMA_ADB_BUFFS_T23X - PVA_NUM_RESERVED_ADB_BUFFERS_T23X)

#define PVA_NUM_DMA_VDB_BUFFS (128U)

#define PVA_NUM_RESERVED_VDB_BUFFERS (0U)

#define PVA_NUM_DYNAMIC_VDB_BUFFS                                              \
	(PVA_NUM_DMA_VDB_BUFFS - PVA_NUM_RESERVED_VDB_BUFFERS)

#define PVA_NUM_VMEM_REGIONS_T23X (3U)

#define PVA_MAX(a, b) ((a) > (b) ? (a) : (b))

#define PVA_MAX_NUM_DYNAMIC_ADB_BUFFS                                          \
	PVA_MAX(PVA_NUM_DYNAMIC_ADB_BUFFS_T26X, PVA_NUM_DYNAMIC_ADB_BUFFS_T23X)

#define PVA_MAX_NUM_ADB_BUFFS                                                  \
	PVA_MAX(PVA_NUM_DMA_ADB_BUFFS_T26X, PVA_NUM_DMA_ADB_BUFFS_T23X)

#define PVA_MAX_NUM_HWSEQ_WORDS                                                \
	PVA_MAX(PVA_NUM_HWSEQ_WORDS_T26X, PVA_NUM_HWSEQ_WORDS_T23X)

#define PVA_MAX_NUM_DMA_CHANNELS                                               \
	PVA_MAX(PVA_DMA_NUM_CHANNELS_T26X, PVA_DMA_NUM_CHANNELS_T23X)

#define PVA_MAX_NUM_DMA_DESC                                                   \
	PVA_MAX(PVA_NUM_DMA_DESC_T26X, PVA_NUM_DMA_DESC_T23X)

#define PVA_MAX_NUM_USER_DMA_DESC                                              \
	MAX(PVA_NUM_USER_DMA_DESC_T26X, PVA_NUM_USER_DMA_DESC_T23X)

#define PVA_NUM_RESERVED_VDB_BUFFERS_L2SRAM_CLEAR (32U)

#define PVA_RESERVED_L2SRAM_CLEAR_VDB_BUFF_START (0u)

#define PVA_KMD_MAX_NUM_DMA_SLOTS 256U
#define PVA_KMD_MAX_NUM_DMA_RELOCS 256U
#define PVA_KMD_MAX_NUM_DMA_DRAM_SLOTS 256U

#define PVA_BL_XBAR_RAW 1
#define PVA_BL_TEGRA_RAW 0
#define PVA_BL_SECTOR_PACK_BIT_SHIFT 39

#define PVA_KMD_CHIP_ID_ENV_VAR "PVA_GEN"
#define PVA_KMD_CHIP_ID_T23X "GEN2"
#define PVA_KMD_CHIP_ID_T26X "GEN3"
#define PVA_KMD_CHIP_ID_DEFAULT PVA_KMD_CHIP_ID_T23X

#define PVA_KMD_TEST_MODE_ENV_VAR "PVA_TEST_MODE"

#define PVA_NS_PER_TSC_TICK_T26X 1U
#define PVA_NS_PER_TSC_TICK_T23X 32U

#define PVA_VERSION_BUFFER_SIZE 256U

#endif // PVA_CONSTANTS_H
