/*
 * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef DCE_CORE_INTERFACE_IPC_TYPES_H
#define DCE_CORE_INTERFACE_IPC_TYPES_H


/*
 * Because this file is to be shared between DCE Core, RM and driver,
 * it must not include or reference anything that is not contained
 * in the following header files:
 *	  stdint.h
 *	  stddef.h
 *	  stdbool.h
 */

typedef uint32_t		dce_ipc_type_t;

#define DCE_IPC_TYPE_ADMIN		((dce_ipc_type_t)0U)
#define DCE_IPC_TYPE_DISPRM		((dce_ipc_type_t)1U)
#define DCE_IPC_TYPE_HDCP		((dce_ipc_type_t)2U)
#define DCE_IPC_TYPE_RM_NOTIFY		((dce_ipc_type_t)3U)
#define DCE_IPC_TYPE_BPMP		((dce_ipc_type_t)4U)
#define DCE_IPC_TYPE_MAX		((dce_ipc_type_t)5U)


#endif
