/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 */

#ifndef __TEGRA_I2S_REGS_H_
#define __TEGRA_I2S_REGS_H_

#define T234_I2S_RX_ENABLE		0x000
#define T234_I2S_RX_SOFT_RESET		0x004
#define T234_I2S_RX_STATUS		0x008
#define T234_I2S_RX_INT_STATUS		0x00c
#define T234_I2S_RX_INT_SET		0x010
#define T234_I2S_RX_INT_MASK		0x014
#define T234_I2S_RX_INT_CLEAR		0x018
#define T234_I2S_RX_FIFO_CTRL		0x01c
#define T234_I2S_RX_FIFO_RD_DATA	0x020
#define T234_I2S_RX_CTRL		0x024
#define T234_I2S_RX_SLOT_CTRL		0x028
#define T234_I2S_RX_CLK_TRIM		0x02c
#define T234_I2S_TX_ENABLE		0x080
#define T234_I2S_TX_SOFT_RESET		0x084
#define T234_I2S_TX_STATUS		0x088
#define T234_I2S_TX_INT_STATUS		0x08c
#define T234_I2S_TX_INT_SET		0x090
#define T234_I2S_TX_INT_MASK		0x094
#define T234_I2S_TX_INT_CLEAR		0x098
#define T234_I2S_TX_FIFO_CTRL		0x09c
#define T234_I2S_TX_FIFO_WR_DATA	0x0a0
#define T234_I2S_TX_START_THRESHOLD	0x0a4
#define T234_I2S_TX_CTRL		0x0a8
#define T234_I2S_TX_SLOT_CTRL		0x0ac
#define T234_I2S_TX_CLK_TRIM		0x0b0
#define T234_I2S_ENABLE			0x100
#define T234_I2S_SOFT_RESET		0x104
#define T234_I2S_CG			0x108
#define T234_I2S_STATUS			0x10c
#define T234_I2S_INT_STATUS		0x110
#define T234_I2S_CTRL			0x114
#define T234_I2S_TIMING			0x118
#define T234_I2S_SLOT_CTRL		0x11c
#define T234_I2S_CLK_TRIM		0x120

/* Fields in T234_I2S_RX_ENABLE */
#define T234_I2S_RX_EN_SHIFT	0
#define T234_I2S_RX_EN		(1 << T234_I2S_RX_EN_SHIFT)

/* Fields in T234_I2S_RX_CTRL */
#define T234_I2S_RX_CTRL_DATA_OFFSET_SHIFT	8
#define T234_I2S_RX_CTRL_DATA_OFFSET_MASK	\
		(0x7ff << T234_I2S_RX_CTRL_DATA_OFFSET_SHIFT)

#define T234_I2S_RX_CTRL_MASK_BITS_SHIFT	4
#define T234_I2S_RX_CTRL_BIT_ORDER_SHIFT	0
#define T234_I2S_RX_CTRL_BIT_ORDER_MASK \
		(1 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)
#define T234_I2S_RX_CTRL_BIT_ORDER_MSB_FIRST \
		(0 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)
#define T234_I2S_RX_CTRL_BIT_ORDER_LSB_FIRST \
		(1 << T234_I2S_RX_CTRL_BIT_ORDER_SHIFT)

/* Fields in T234_I2S_TX_ENABLE */
#define T234_I2S_TX_EN_SHIFT	0
#define T234_I2S_TX_EN		(1 << T234_I2S_TX_EN_SHIFT)

/* Fields in T234_I2S_TX_CTRL */
#define T234_I2S_TX_CTRL_DATA_OFFSET_SHIFT	8
#define T234_I2S_TX_CTRL_DATA_OFFSET_MASK	\
		(0x7ff << T234_I2S_TX_CTRL_DATA_OFFSET_SHIFT)

#define T234_I2S_TX_CTRL_MASK_BITS_SHIFT	4

#define T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT	1
#define T234_I2S_TX_CTRL_HIGHZ_CTRL_MASK \
		(3 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define T234_I2S_TX_CTRL_HIGHZ_CTRL_NOHIGHZ \
		(0 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define T234_I2S_TX_CTRL_HIGHZ_CTRL_HIGHZ \
		(1 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)
#define T234_I2S_TX_CTRL_HIGHZ_CTRL_HIGHZ_ON_HALF_BIT_CLK \
		(2 << T234_I2S_TX_CTRL_HIGHZ_CTRL_SHIFT)

#define T234_I2S_TX_CTRL_BIT_ORDER_SHIFT	0
#define T234_I2S_TX_CTRL_BIT_ORDER_MASK \
		(1 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)
#define T234_I2S_TX_CTRL_BIT_ORDER_MSB_FIRST \
		(0 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)
#define T234_I2S_TX_CTRL_BIT_ORDER_LSB_FIRST \
		(1 << T234_I2S_TX_CTRL_BIT_ORDER_SHIFT)

/* Fields in T234_I2S_ENABLE */
#define T234_I2S_EN_SHIFT			0
#define T234_I2S_EN_MASK			(1 << T234_I2S_EN_SHIFT)
#define T234_I2S_EN				(1 << T234_I2S_EN_SHIFT)

/* Fields in T234_I2S_CTRL */
#define T234_I2S_CTRL_FSYNC_WIDTH_SHIFT		16
#define T234_I2S_CTRL_FSYNC_WIDTH_MASK \
		(0xff << T234_I2S_CTRL_FSYNC_WIDTH_SHIFT)

#define T234_I2S_POS_EDGE			0
#define T234_I2S_NEG_EDGE			1
#define T234_I2S_CTRL_EDGE_CTRL_SHIFT		10
#define T234_I2S_CTRL_EDGE_CTRL_MASK \
	(1 << T234_I2S_CTRL_EDGE_CTRL_SHIFT)
#define T234_I2S_CTRL_EDGE_CTRL_POS_EDGE \
	(T234_I2S_POS_EDGE << T234_I2S_CTRL_EDGE_CTRL_SHIFT)
#define T234_I2S_CTRL_EDGE_CTRL_NEG_EDGE \
	(T234_I2S_NEG_EDGE << T234_I2S_CTRL_EDGE_CTRL_SHIFT)

#define T234_I2S_CTRL_PIPE_MACRO_EN_SHIFT	9
#define T234_I2S_CTRL_PIPE_MACRO_EN \
		(1 << T234_I2S_CTRL_PIPE_MACRO_EN_SHIFT)

#define T234_I2S_FRAME_FORMAT_LRCK		0
#define T234_I2S_FRAME_FORMAT_FSYNC		1
#define T234_I2S_CTRL_FRAME_FORMAT_SHIFT	6
#define T234_I2S_CTRL_FRAME_FORMAT_MASK \
	(7 << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)
#define T234_I2S_CTRL_FRAME_FORMAT_LRCK_MODE \
	(T234_I2S_FRAME_FORMAT_LRCK << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)
#define T234_I2S_CTRL_FRAME_FORMAT_FSYNC_MODE \
	(T234_I2S_FRAME_FORMAT_FSYNC << T234_I2S_CTRL_FRAME_FORMAT_SHIFT)

#define T234_I2S_CTRL_MASTER_EN_SHIFT		5
#define T234_I2S_CTRL_MASTER_EN_MASK \
			(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)
#define T234_I2S_CTRL_MASTER_EN \
			(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)
#define T234_I2S_CTRL_SLAVE_EN \
			(1 << T234_I2S_CTRL_MASTER_EN_SHIFT)

#define T234_I2S_CTRL_LRCK_POLARITY_SHIFT	4
#define T234_I2S_CTRL_LRCK_POLARITY_MASK \
			(1 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)
#define T234_I2S_CTRL_LRCK_POLARITY_LOW \
			(0 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)
#define T234_I2S_CTRL_LRCK_POLARITY_HIGH \
			(1 << T234_I2S_CTRL_LRCK_POLARITY_SHIFT)

#define T234_I2S_CTRL_LPBK_SHIFT		3
#define T234_I2S_CTRL_LPBK_MASK		(1 << T234_I2S_CTRL_LPBK_SHIFT)
#define T234_I2S_CTRL_LPBK_EN		(1 << T234_I2S_CTRL_LPBK_SHIFT)

#define T234_I2S_BITS_8				1
#define T234_I2S_BITS_12			2
#define T234_I2S_BITS_16			3
#define T234_I2S_BITS_20			4
#define T234_I2S_BITS_24			5
#define T234_I2S_BITS_28			6
#define T234_I2S_BITS_32			7
#define T234_I2S_CTRL_BIT_SIZE_SHIFT		0
#define T234_I2S_CTRL_BIT_SIZE_MASK \
		(7 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_8 \
		(T234_I2S_BITS_8	<< T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_12 \
		(T234_I2S_BITS_12 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_16 \
		(T234_I2S_BITS_16 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_20 \
		(T234_I2S_BITS_20 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_24 \
		(T234_I2S_BITS_24 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_28 \
		(T234_I2S_BITS_28 << T234_I2S_CTRL_BIT_SIZE_SHIFT)
#define T234_I2S_CTRL_BIT_SIZE_32 \
		(T234_I2S_BITS_32 << T234_I2S_CTRL_BIT_SIZE_SHIFT)

/* Fields in T234_I2S_TIMING */
#define T234_I2S_TIMING_NON_SYM_EN_SHIFT	12
#define T234_I2S_TIMING_NON_SYM_EN \
				(1 << T234_I2S_TIMING_NON_SYM_EN_SHIFT)
#define T234_I2S_TIMING_CHANNEL_BIT_CNT_MASK	0x3ff
#define T234_I2S_TIMING_CHANNEL_BIT_CNT_SHIFT	0

/* Fields in T234_I2S_RX_SOFT_RESET */
#define T234_I2S_RX_SOFT_RESET_SHIFT		0
#define T234_I2S_RX_SOFT_RESET_MASK \
				(1 << T234_I2S_RX_SOFT_RESET_SHIFT)
#define T234_I2S_RX_SOFT_RESET_EN \
				(1 << T234_I2S_RX_SOFT_RESET_SHIFT)
#define T234_I2S_RX_SOFT_RESET_DEFAULT \
				(0 << T234_I2S_RX_SOFT_RESET_SHIFT)

#define T234_I2S_SCLK_TRIM_SEL_SHIFT		8
#define T234_I2S_SCLK_TRIM_SEL_MASK		0x1F

/* Fields in T234_I2S_RX_STATUS */
#define T234_I2S_RX_STATUS_ENABLED_SHIFT	0
#define T234_I2S_RX_STATUS_ENABLED \
				(1 << T234_I2S_RX_STATUS_ENABLED_SHIFT)
#define T234_I2S_RX_STATUS_FIFO_EMPTY_SHIFT	1
#define T234_I2S_RX_STATUS_FIFO_EMPTY \
				(1 << T234_I2S_RX_STATUS_FIFO_EMPTY_SHIFT)
#define T234_I2S_RX_STATUS_FIFO_FULL_SHIFT	2
#define T234_I2S_RX_STATUS_FIFO_FULL \
				(1 << T234_I2S_RX_STATUS_FIFO_FULL_SHIFT)
#define T234_I2S_RX_STATUS_FIFO_COUNT_SHIFT	8
#define T234_I2S_RX_STATUS_FIFO_COUNT_MASK \
				(0x7f << T234_I2S_RX_STATUS_FIFO_COUNT_SHIFT)

/* Fields in T234_I2S_TX_STATUS */
#define T234_I2S_TX_STATUS_ENABLED_SHIFT	0
#define T234_I2S_TX_STATUS_ENABLED \
				(1 << T234_I2S_TX_STATUS_ENABLED_SHIFT)
#define T234_I2S_TX_STATUS_FIFO_EMPTY_SHIFT	1
#define T234_I2S_TX_STATUS_FIFO_EMPTY \
				(1 << T234_I2S_TX_STATUS_FIFO_EMPTY_SHIFT)
#define T234_I2S_TX_STATUS_FIFO_FULL_SHIFT	2
#define T234_I2S_TX_STATUS_FIFO_FULL \
				(1 << T234_I2S_TX_STATUS_FIFO_FULL_SHIFT)
#define T234_I2S_TX_STATUS_FIFO_COUNT_SHIFT	8
#define T234_I2S_TX_STATUS_FIFO_COUNT_MASK \
				(0x7f << T234_I2S_TX_STATUS_FIFO_COUNT_SHIFT)

/* Fields in T234_I2S_TX_SOFT_RESET */
#define T234_I2S_TX_SOFT_RESET_SHIFT		0
#define T234_I2S_TX_SOFT_RESET_MASK \
				(1 << T234_I2S_TX_SOFT_RESET_SHIFT)
#define T234_I2S_TX_SOFT_RESET_EN \
				(1 << T234_I2S_TX_SOFT_RESET_SHIFT)
#define T234_I2S_TX_SOFT_RESET_DEFAULT \
				(0 << T234_I2S_TX_SOFT_RESET_SHIFT)

/* Fields in T234_I2S_SLOT_CTRL */
#define T234_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT	0
#define T234_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK	0xf

/* Fields in T234_I2S_TX_SLOT_CTRL */
#define T234_I2S_TX_SLOT_CTRL_SLOT_ENABLES_SHIFT	0
#define T234_I2S_TX_SLOT_CTRL_SLOT_ENABLES_MASK		0xffff

/* Fields in T234_I2S_RX_SLOT_CTRL */
#define T234_I2S_RX_SLOT_CTRL_SLOT_ENABLES_SHIFT	0
#define T234_I2S_RX_SLOT_CTRL_SLOT_ENABLES_MASK		0xffff

#endif /* _TEGRA_I2S_REGS_H_ */
