// SPDX-License-Identifier: GPL-2.0-only
/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 *
 * Tegra TSEC Module Support
 */

#ifndef TSEC_COMMS_CMDS_H
#define TSEC_COMMS_CMDS_H

struct RM_FLCN_QUEUE_HDR {
	u8      unitId;
	u8      size;
	u8      ctrlFlags;
	u8      seqNumId;
};

#define RM_FLCN_QUEUE_HDR_SIZE          sizeof(struct RM_FLCN_QUEUE_HDR)


#define RM_GSP_UNIT_REWIND      (0x00)
#define RM_GSP_UNIT_INIT        (0x02)
#define RM_GSP_UNIT_HDCP22WIRED (0x06)
#define RM_GSP_UNIT_END         (0x11)

#define RM_GSP_LOG_QUEUE_NUM    (2)

#define RM_FLCN_HDCP22_CMD_ID_GET_CONTEXT (8)
#define RM_FLCN_HDCP22_MSG_ID_GET_CONTEXT (8)

struct RM_GSP_INIT_MSG_GSP_INIT {
	u8      msgType;
	u8      numQueues;
	u16     osDebugEntryPoint;
	struct {
		u32     queueOffset;
		u16     queueSize;
		u8      queuePhyId;
		u8      queueLogId;
	} qInfo[RM_GSP_LOG_QUEUE_NUM];
	u32     rsvd1;
	u8      rsvd2;
	u8      status;
};

struct RM_FLCN_U64 {
	u32 lo;
	u32 hi;
};

struct RM_FLCN_MEM_DESC {
	struct RM_FLCN_U64 address;
	u32                params;
};


struct RM_FLCN_HDCP22_CMD_GET_CONTEXT {
	struct RM_FLCN_QUEUE_HDR   hdr;          //<! hdr
	u8                         cmdType;      //<! RM_FLCN_HDCP22_CMD_ID_GET_CONTEXT
	u8                         reserved[3];  //<! padding
	struct RM_FLCN_MEM_DESC    context;      //<! DMA pointer for the context info
};

enum RM_FLCN_HDCP22_STATUS {
	RM_FLCN_HDCP22_STATUS_ERROR_NULL = 0,
	RM_FLCN_HDCP22_STATUS_ERROR_ENC_ACTIVE,
	RM_FLCN_HDCP22_STATUS_ERROR_FLCN_BUSY,
	RM_FLCN_HDCP22_STATUS_ERROR_TYPE1_LOCK_ACTIVE,
	RM_FLCN_HDCP22_STATUS_ERROR_INIT_SESSION_FAILED,
	RM_FLCN_HDCP22_STATUS_ERROR_AKE_INIT,
	RM_FLCN_HDCP22_STATUS_ERROR_CERT_RX,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_CERT_RX,
	RM_FLCN_HDCP22_STATUS_ERROR_MASTER_KEY_EXCHANGE,
	RM_FLCN_HDCP22_STATUS_ERROR_H_PRIME,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_H_PRIME,
	RM_FLCN_HDCP22_STATUS_ERROR_PAIRING,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_PAIRING,
	RM_FLCN_HDCP22_STATUS_ERROR_LC_INIT,
	RM_FLCN_HDCP22_STATUS_ERROR_L_PRIME,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_L_PRIME,
	RM_FLCN_HDCP22_STATUS_ERROR_SKE_INIT,
	RM_FLCN_HDCP22_STATUS_ERROR_SET_STREAM_TYPE,
	RM_FLCN_HDCP22_STATUS_ERROR_EN_ENC,
	RM_FLCN_HDCP22_STATUS_ERROR_RPTR_INIT,
	RM_FLCN_HDCP22_STATUS_ERROR_RPTR_STREAM_MNT,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_RXID_LIST,
	RM_FLCN_HDCP22_STATUS_ERROR_RPTR_MPRIME,
	RM_FLCN_HDCP22_STATUS_TIMEOUT_MPRIME,
	RM_FLCN_HDCP22_STATUS_ENC_ENABLED,
	RM_FLCN_HDCP22_STATUS_INIT_SECONDARY_LINK,
	RM_FLCN_HDCP22_STATUS_RPTR_STARTED,
	RM_FLCN_HDCP22_STATUS_RPTR_DONE,
	RM_FLCN_HDCP22_STATUS_REAUTH_REQ,
	RM_FLCN_HDCP22_STATUS_MONITOR_OFF_SUCCESS,
	RM_FLCN_HDCP22_STATUS_VALID_SRM,
	RM_FLCN_HDCP22_STATUS_ERROR_INVALID_SRM,
	RM_FLCN_HDCP22_STATUS_TEST_SE_SUCCESS,
	RM_FLCN_HDCP22_STATUS_TEST_SE_FAILURE,
	RM_FLCN_HDCP22_STATUS_WRITE_DP_ECF_SUCCESS,
	RM_FLCN_HDCP22_STATUS_WRITE_DP_ECF_FAILURE,
	RM_FLCN_HDCP22_STATUS_ERROR_NOT_SUPPORTED,
	RM_FLCN_HDCP22_STATUS_ERROR_HPD,
	RM_FLCN_HDCP22_STATUS_VALIDATE_STREAM_SUCCESS,
	RM_FLCN_HDCP22_STATUS_ERROR_VALIDATE_STREAM_FAILURE,
	RM_FLCN_HDCP22_STATUS_ERROR_STREAM_INVALID,
	RM_FLCN_HDCP22_STATUS_ERROR_ILLEGAL_TIMEREVENT,
	RM_FLCN_HDCP22_STATUS_FLUSH_TYPE_SUCCESS,
	RM_FLCN_HDCP22_STATUS_FLUSH_TYPE_FAILURE,
	RM_FLCN_HDCP22_STATUS_FLUSH_TYPE_LOCK_ACTIVE,
	RM_FLCN_HDCP22_STATUS_FLUSH_TYPE_IN_PROGRESS,
	RM_FLCN_HDCP22_STATUS_ERROR_REGISTER_RW,
	RM_FLCN_HDCP22_STATUS_INVALID_ARGUMENT,
	RM_FLCN_HDCP22_STATUS_ERROR_INTEGRITY_CHECK_FAILURE,
	RM_FLCN_HDCP22_STATUS_ERROR_INTEGRITY_UPDATE_FAILURE,
	RM_FLCN_HDCP22_STATUS_ERROR_DISABLE_WITH_LANECNT0,
	RM_FLCN_HDCP22_STATUS_ERROR_START_TIMER,
	RM_FLCN_HDCP22_STATUS_ERROR_HWDRM_WAR_AUTH_FAILURE,
	RM_FLCN_HDCP22_STATUS_ERROR_START_SESSION,
	RM_FLCN_HDCP22_STATUS_MAKE_ENUM_32_BIT = 0xFFFFFFFFU,
};

struct RM_FLCN_HDCP22_MSG_GENERIC {
	u8 msgType;
	enum RM_FLCN_HDCP22_STATUS flcnStatus;
	u8 streamType;
};

#endif /* TSEC_COMMS_CMDS_H */
