/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
 */

#ifndef PVA_DMA_H
#define PVA_DMA_H

#include "pva_queue.h"

enum nvpva_task_dma_trig_vpu_hw_events {
	TRIG_VPU_NO_TRIGGER,
	TRIG_VPU_DMA_READ0_START,
	TRIG_VPU_DMA_STORE0_START,
	TRIG_VPU_CONFIG_START,
	TRIG_VPU_DMA_READ1_START,
	TRIG_VPU_DMA_STORE1_START,
	TRIG_VPU_DMA_READ2_START,
	TRIG_VPU_DMA_STORE2_START,
	TRIG_VPU_DMA_READ3_START,
	TRIG_VPU_DMA_STORE3_START,
	TRIG_VPU_DMA_READ4_START,
	TRIG_VPU_DMA_STORE4_START,
	TRIG_VPU_DMA_READ5_START,
	TRIG_VPU_DMA_STORE5_START,
	TRIG_VPU_DMA_READ6_START,
	TRIG_VPU_DMA_STORE6_START
};

enum nvpva_dma_trig_event_mode {
	TRIG_EVENT_MODE_DISABLED,
	TRIG_EVENT_MODE_DIM4,
	TRIG_EVENT_MODE_DIM3,
	TRIG_EVENT_MODE_TILE
};

enum nvpva_task_dma_src_xfer_mode {
	DMA_DESC_SRC_XFER_INVAL = 0U,
	DMA_DESC_SRC_XFER_MC = 1U,
	DMA_DESC_SRC_XFER_VMEM = 2U,
	DMA_DESC_SRC_XFER_L2RAM = 3U,
	DMA_DESC_SRC_XFER_R5TCM = 4U,
	DMA_DESC_SRC_XFER_MMIO = 5U,
	DMA_DESC_SRC_XFER_RSVD = 6U,
	DMA_DESC_SRC_XFER_VPU_CONFIG = 7U,
};

enum nvpva_task_dma_dst_xfer_mode {
	DMA_DESC_DST_XFER_INVAL = 0U,
	DMA_DESC_DST_XFER_MC = 1U,
	DMA_DESC_DST_XFER_VMEM = 2U,
	DMA_DESC_DST_XFER_L2RAM = 3U,
	DMA_DESC_DST_XFER_R5TCM = 4U,
	DMA_DESC_DST_XFER_MMIO = 5U,
	DMA_DESC_DST_XFER_RSVD1 = 6U,
	DMA_DESC_DST_XFER_RSVD2 = 7U,
};

/* signals generated by channel */
enum pva_dma_chan_sig {
	PVA_DMA_READ0 = 0x0001,
	PVA_DMA_STORE0 = 0x0002,
	PVA_DMA_READ1 = 0x0004,
	PVA_DMA_STORE1 = 0x0008,
	PVA_DMA_READ2 = 0x0010,
	PVA_DMA_STORE2 = 0x0020,
	PVA_DMA_READ3 = 0x0040,
	PVA_DMA_STORE3 = 0x0080,
	PVA_DMA_READ4 = 0x0100,
	PVA_DMA_STORE4 = 0x0200,
	PVA_DMA_READ5 = 0x0400,
	PVA_DMA_STORE5 = 0x0800,
	PVA_DMA_READ6 = 0x1000,
	PVA_DMA_STORE6 = 0x2000,
	PVA_VPUCONFIG = 0x4000,
	PVA_HWSEQ_VPUREAD_START = 0x8000,
	PVA_HWSEQ_VPUWRITE_START = 0x10000
};

int pva_task_write_dma_info(struct pva_submit_task *task,
			    struct pva_hw_task *hw_task);

int pva_task_write_dma_misr_info(struct pva_submit_task *task,
			    struct pva_hw_task *hw_task);
#endif
