From 01b31bbabbf4da540bd4b1b5f28b72ad02c9d2ed Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 1 Oct 2024 04:47:17 +0000 Subject: [PATCH] memory: tegra: Update allowlist of PERFMUX registers Add few PERFMUX register offsets to allowlist for SOC-HWPM to access. Bug 4704678 Change-Id: Ica7c6d2a7fc47699abf0969eef1b4b4a518a5b78 Signed-off-by: Ashish Mhetre Reviewed-on: https://git-master.nvidia.com/r/c/linux-t264/+/3221623 Reviewed-by: Sachin Nikam Reviewed-by: Pritesh Raithatha GVS: buildbot_gerritrpt --- drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c b/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c index 7024f51f..7b27fd58 100644 --- a/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c +++ b/drivers/memory/tegra/private-soc/tegra264-mc-hwpm.c @@ -18,6 +18,9 @@ #define MC_MCC_CTL_PERFMUX_OFFSET 0x8914 #define MC_MCC_DP_PERFMUX_OFFSET 0x8918 #define MC_CBRIDGE_PERFMUX_OFFSET 0x891c +#define MSS_HUB_IB_PERFMUX_OFFSET 0x6f3c +#define MSS_HUB_CIF_PERFMUX_OFFSET 0x6f34 +#define MSS_HUB_TU_PERFMUX_0 0x6f38 #define MAX_MC_CHANNELS 17 // Broadcast Channel + 16 MC Channels @@ -66,7 +69,8 @@ static int tegra_mc_hwpm_reg_op(void *ip_dev, } if (reg_offset != MC_MCC_CTL_PERFMUX_OFFSET && reg_offset != MC_MCC_DP_PERFMUX_OFFSET && - reg_offset != MC_CBRIDGE_PERFMUX_OFFSET) { + reg_offset != MC_CBRIDGE_PERFMUX_OFFSET && reg_offset != MSS_HUB_IB_PERFMUX_OFFSET && + reg_offset != MSS_HUB_CIF_PERFMUX_OFFSET && reg_offset != MSS_HUB_TU_PERFMUX_0) { dev_err(dev, "SOC-HWPM requesting access to prohibited register"); return -EPERM; }