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drm/tegra: Merge upstream changes
Merge upstream changes from linux-next, including merged version of new UAPI. Change-Id: I4f591d39e51ac6ab6877a0bd428adf166eca3c55 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2653095 Tested-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
Mikko Perttunen
committed by
Laxman Dewangan
Laxman Dewangan
parent
a6ff2bcf9e
commit
02b028d02a
254
drivers/gpu/drm/tegra/firewall.c
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254
drivers/gpu/drm/tegra/firewall.c
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@@ -0,0 +1,254 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2010-2020 NVIDIA Corporation */
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#include "drm.h"
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#include "submit.h"
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#include "uapi.h"
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struct tegra_drm_firewall {
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struct tegra_drm_submit_data *submit;
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struct tegra_drm_client *client;
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u32 *data;
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u32 pos;
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u32 end;
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u32 class;
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};
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static int fw_next(struct tegra_drm_firewall *fw, u32 *word)
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{
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if (fw->pos == fw->end)
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return -EINVAL;
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*word = fw->data[fw->pos++];
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return 0;
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}
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static bool fw_check_addr_valid(struct tegra_drm_firewall *fw, u32 offset)
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{
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u32 i;
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for (i = 0; i < fw->submit->num_used_mappings; i++) {
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struct tegra_drm_mapping *m = fw->submit->used_mappings[i].mapping;
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if (offset >= m->iova && offset <= m->iova_end)
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return true;
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}
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return false;
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}
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static int fw_check_reg(struct tegra_drm_firewall *fw, u32 offset)
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{
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bool is_addr;
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u32 word;
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int err;
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err = fw_next(fw, &word);
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if (err)
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return err;
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if (!fw->client->ops->is_addr_reg)
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return 0;
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is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
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offset);
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if (!is_addr)
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return 0;
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if (!fw_check_addr_valid(fw, word))
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return -EINVAL;
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return 0;
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}
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static int fw_check_regs_seq(struct tegra_drm_firewall *fw, u32 offset,
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u32 count, bool incr)
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{
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u32 i;
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for (i = 0; i < count; i++) {
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if (fw_check_reg(fw, offset))
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return -EINVAL;
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if (incr)
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offset++;
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}
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return 0;
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}
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static int fw_check_regs_mask(struct tegra_drm_firewall *fw, u32 offset,
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u16 mask)
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{
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unsigned long bmask = mask;
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unsigned int bit;
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for_each_set_bit(bit, &bmask, 16) {
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if (fw_check_reg(fw, offset+bit))
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return -EINVAL;
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}
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return 0;
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}
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static int fw_check_regs_imm(struct tegra_drm_firewall *fw, u32 offset)
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{
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bool is_addr;
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is_addr = fw->client->ops->is_addr_reg(fw->client->base.dev, fw->class,
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offset);
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if (is_addr)
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return -EINVAL;
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return 0;
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}
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static int fw_check_class(struct tegra_drm_firewall *fw, u32 class)
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{
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if (!fw->client->ops->is_valid_class) {
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if (class == fw->client->base.class)
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return 0;
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else
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return -EINVAL;
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}
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if (!fw->client->ops->is_valid_class(class))
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return -EINVAL;
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return 0;
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}
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enum {
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HOST1X_OPCODE_SETCLASS = 0x00,
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HOST1X_OPCODE_INCR = 0x01,
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HOST1X_OPCODE_NONINCR = 0x02,
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HOST1X_OPCODE_MASK = 0x03,
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HOST1X_OPCODE_IMM = 0x04,
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HOST1X_OPCODE_RESTART = 0x05,
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HOST1X_OPCODE_GATHER = 0x06,
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HOST1X_OPCODE_SETSTRMID = 0x07,
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HOST1X_OPCODE_SETAPPID = 0x08,
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HOST1X_OPCODE_SETPYLD = 0x09,
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HOST1X_OPCODE_INCR_W = 0x0a,
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HOST1X_OPCODE_NONINCR_W = 0x0b,
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HOST1X_OPCODE_GATHER_W = 0x0c,
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HOST1X_OPCODE_RESTART_W = 0x0d,
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HOST1X_OPCODE_EXTEND = 0x0e,
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};
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int tegra_drm_fw_validate(struct tegra_drm_client *client, u32 *data, u32 start,
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u32 words, struct tegra_drm_submit_data *submit,
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u32 *job_class)
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{
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struct tegra_drm_firewall fw = {
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.submit = submit,
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.client = client,
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.data = data,
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.pos = start,
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.end = start+words,
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.class = *job_class,
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};
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bool payload_valid = false;
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u32 payload;
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int err;
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while (fw.pos != fw.end) {
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u32 word, opcode, offset, count, mask, class;
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err = fw_next(&fw, &word);
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if (err)
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return err;
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opcode = (word & 0xf0000000) >> 28;
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switch (opcode) {
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case HOST1X_OPCODE_SETCLASS:
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offset = word >> 16 & 0xfff;
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mask = word & 0x3f;
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class = (word >> 6) & 0x3ff;
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err = fw_check_class(&fw, class);
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fw.class = class;
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*job_class = class;
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if (!err)
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err = fw_check_regs_mask(&fw, offset, mask);
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if (err)
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dev_warn(client->base.dev,
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"illegal SETCLASS(offset=0x%x, mask=0x%x, class=0x%x) at word %u",
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offset, mask, class, fw.pos-1);
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break;
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case HOST1X_OPCODE_INCR:
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offset = (word >> 16) & 0xfff;
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count = word & 0xffff;
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err = fw_check_regs_seq(&fw, offset, count, true);
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if (err)
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dev_warn(client->base.dev,
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"illegal INCR(offset=0x%x, count=%u) in class 0x%x at word %u",
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offset, count, fw.class, fw.pos-1);
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break;
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case HOST1X_OPCODE_NONINCR:
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offset = (word >> 16) & 0xfff;
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count = word & 0xffff;
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err = fw_check_regs_seq(&fw, offset, count, false);
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if (err)
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dev_warn(client->base.dev,
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"illegal NONINCR(offset=0x%x, count=%u) in class 0x%x at word %u",
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offset, count, fw.class, fw.pos-1);
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break;
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case HOST1X_OPCODE_MASK:
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offset = (word >> 16) & 0xfff;
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mask = word & 0xffff;
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err = fw_check_regs_mask(&fw, offset, mask);
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if (err)
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dev_warn(client->base.dev,
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"illegal MASK(offset=0x%x, mask=0x%x) in class 0x%x at word %u",
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offset, mask, fw.class, fw.pos-1);
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break;
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case HOST1X_OPCODE_IMM:
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/* IMM cannot reasonably be used to write a pointer */
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offset = (word >> 16) & 0xfff;
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err = fw_check_regs_imm(&fw, offset);
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if (err)
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dev_warn(client->base.dev,
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"illegal IMM(offset=0x%x) in class 0x%x at word %u",
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offset, fw.class, fw.pos-1);
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break;
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case HOST1X_OPCODE_SETPYLD:
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payload = word & 0xffff;
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payload_valid = true;
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break;
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case HOST1X_OPCODE_INCR_W:
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if (!payload_valid)
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return -EINVAL;
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offset = word & 0x3fffff;
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err = fw_check_regs_seq(&fw, offset, payload, true);
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if (err)
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dev_warn(client->base.dev,
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"illegal INCR_W(offset=0x%x) in class 0x%x at word %u",
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offset, fw.class, fw.pos-1);
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break;
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case HOST1X_OPCODE_NONINCR_W:
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if (!payload_valid)
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return -EINVAL;
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offset = word & 0x3fffff;
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err = fw_check_regs_seq(&fw, offset, payload, false);
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if (err)
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dev_warn(client->base.dev,
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"illegal NONINCR(offset=0x%x) in class 0x%x at word %u",
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offset, fw.class, fw.pos-1);
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break;
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default:
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dev_warn(client->base.dev, "illegal opcode at word %u",
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fw.pos-1);
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return -EINVAL;
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}
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if (err)
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return err;
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}
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return 0;
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}
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