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video: tegra: virt: separate dev and dt for init

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The dt node that includes ivc properties and the dev does not have to be
same node. GPU could be PCIE endpoint device which does not have
corresponding dt node, so GPU driver uses PCIE controller node to store
ivc properties.

Jira GVSCI-15779

Change-Id: Ibf9c8f17eac1accceee5fe8d5eca3521cda934b9
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2884313
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Richard Zhao
2023-04-06 23:05:56 -07:00
committed by mobile promotions
parent be01df015d
commit 054f2a1a22
2 changed files with 16 additions and 20 deletions
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4
include/linux/tegra_gr_comm.h
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@@ -8,11 +8,11 @@
#ifndef __TEGRA_GR_COMM_H
#define __TEGRA_GR_COMM_H
#include <linux/platform_device.h>
#include <linux/device.h>
#define TEGRA_GR_COMM_ID_SELF (0xFF)
int tegra_gr_comm_init(struct platform_device *pdev, u32 elems,
int tegra_gr_comm_init(struct device *dev, struct device_node *dn, u32 elems,
const size_t *queue_sizes, u32 queue_start, u32 num_queues);
void tegra_gr_comm_deinit(u32 queue_start, u32 num_queues);
int tegra_gr_comm_send(u32 peer, u32 index, void *data,