diff --git a/drivers/scsi/ufs/ufs-tegra-common.c b/drivers/scsi/ufs/ufs-tegra-common.c index 00b0d789..c06837f4 100644 --- a/drivers/scsi/ufs/ufs-tegra-common.c +++ b/drivers/scsi/ufs/ufs-tegra-common.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. #include @@ -47,27 +47,23 @@ #define NON_RDL_STRUCTURE 0x90570c8 #define NON_RDL_LEAD 0x83c1002 -static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra); - -static int mphy_go_bit_status(void __iomem *mphy_base, u32 offset) { - +static int mphy_go_bit_status(void __iomem *mphy_base, u32 offset) +{ unsigned int timeout; unsigned int err = 0; u32 mphy_rx_vendor2 = 0; timeout = 500U; /* Number of iterations */ while (timeout != 0U) { - mphy_rx_vendor2 = mphy_readl(mphy_base, offset); - if ((mphy_rx_vendor2 & MPHY_GO_BIT) == 0U) { - break; - } else { - udelay(1); - } + mphy_rx_vendor2 = mphy_readl(mphy_base, offset); + if ((mphy_rx_vendor2 & MPHY_GO_BIT) == 0U) + break; + udelay(1); timeout--; } - if (timeout == 0U) { + if (timeout == 0U) err = -ETIMEDOUT; - } + return err; } @@ -101,7 +97,7 @@ static void ufs_tegra_set_clk_div(struct ufs_hba *hba) ufshcd_writel(hba, UFS_VNDR_HCLKDIV_1US_TICK_FPGA, REG_UFS_VNDR_HCLKDIV); else ufshcd_writel(hba, hclk_val, REG_UFS_VNDR_HCLKDIV); - udelay(20); + ufshcd_delay_us(20, 10); } static void ufs_tegra_ufs_mmio_axi(struct ufs_hba *hba) @@ -112,11 +108,10 @@ static void ufs_tegra_ufs_mmio_axi(struct ufs_hba *hba) return; ufshcd_rmwl(hba, mask, VS_BURSTMBLCONFIG, VS_BURSTMBLREGISTER); - } static int ufs_tegra_host_clk_get(struct device *dev, - const char *name, struct clk **clk_out) + const char *name, struct clk **clk_out) { struct clk *clk; int err = 0; @@ -139,7 +134,7 @@ static int ufs_tegra_host_clk_get(struct device *dev, } static int ufs_tegra_host_clk_enable(struct device *dev, - const char *name, struct clk *clk) + const char *name, struct clk *clk) { int err = 0; @@ -164,7 +159,6 @@ static int ufs_tegra_mphy_receiver_calibration(struct ufs_tegra_host *ufs_tegra, { int err = 0; struct device *dev = ufs_tegra->hba->dev; - u32 mphy_rx_vendor2_reg; u32 mphy_rx_vendor2; unsigned int timeout; @@ -176,194 +170,132 @@ static int ufs_tegra_mphy_receiver_calibration(struct ufs_tegra_host *ufs_tegra, if (tegra_sku_info.platform == TEGRA_PLATFORM_VSP) return 0; - if (ufs_tegra->enable_mphy_rx_calib) - return 0; + /* Set RX lane calibration */ + if (ufs_tegra->x2config) { + dev_dbg(dev, "%s:x2config is true so invoking mphy_update\n", + __func__); + mphy_update(ufs_tegra->mphy_l1_base, + MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, + MPHY_RX_APB_VENDOR2_0_T234); + mphy_update(ufs_tegra->mphy_l1_base, + MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) { + dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); + goto fail; + } + } - if (ufs_tegra->soc->chip_id >= TEGRA234) { - mphy_rx_vendor2_reg = MPHY_RX_APB_VENDOR2_0_T234; - } else { - mphy_rx_vendor2_reg = MPHY_RX_APB_VENDOR2_0; - } + mphy_update(ufs_tegra->mphy_l0_base, + MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, MPHY_RX_APB_VENDOR2_0_T234); + mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, + MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) { + dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); + goto fail; + } - if (ufs_tegra->soc->chip_id >= TEGRA234) { - /* Set RX lane calibration */ - if (ufs_tegra->x2config == true) { - dev_dbg(dev, "%s:x2config is true so invoking mphy_update\n", - __func__); - mphy_update(ufs_tegra->mphy_l1_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, - mphy_rx_vendor2_reg); - /* TODO: GO bit has to be read back after updating it */ - mphy_update(ufs_tegra->mphy_l1_base, - MPHY_GO_BIT, mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, mphy_rx_vendor2_reg); - if (err) { - dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - goto fail; + if (ufs_tegra->x2config) { + /* Wait till lane calibration is done */ + timeout = 100U; /* Number of iterations */ + while (timeout != 0U) { + mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l1_base, + MPHY_RX_APB_VENDOR2_0_T234); + + if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) != 0U) { + dev_dbg(dev, + "%s: MPhy Receiver Calibration passed\n", __func__); + break; } + udelay(1); + timeout--; + } + if (timeout == 0U) { + dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); + err = -ETIMEDOUT; + goto fail; } - mphy_update(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, mphy_rx_vendor2_reg); - /* TODO: GO bit has to be read back after updating it */ - mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, - mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, mphy_rx_vendor2_reg); - if (err) { - dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); + /* Clear RX lane calibration */ + mphy_clear_bits(ufs_tegra->mphy_l1_base, + MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, + MPHY_RX_APB_VENDOR2_0_T234); + mphy_update(ufs_tegra->mphy_l1_base, + MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) { + dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); goto fail; - } + } - if (ufs_tegra->x2config == true) { - /* Wait till lane calibration is done */ - timeout = 100U; /* Number of iterations */ - while (timeout != 0U) { - mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l1_base, - mphy_rx_vendor2_reg); + /* Wait till lane calibration is done */ + timeout = 100U; /* Number of iterations */ + while (timeout != 0U) { + mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l1_base, + MPHY_RX_APB_VENDOR2_0_T234); - if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) != 0U) { - dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", __func__); - break; - } else { - udelay(1); - } - timeout--; - } - if (timeout == 0U) { - dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); - err = -ETIMEDOUT; - goto fail; - } - - /* Clear RX lane calibration */ - mphy_clear_bits(ufs_tegra->mphy_l1_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, - mphy_rx_vendor2_reg); - mphy_update(ufs_tegra->mphy_l1_base, - MPHY_GO_BIT, mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, mphy_rx_vendor2_reg); - if (err) { - dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - goto fail; + if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) == 0U) { + dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", + __func__); + break; } - - /* Wait till lane calibration is done */ - timeout = 100U; /* Number of iterations */ - while (timeout != 0U) { - mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l1_base, - mphy_rx_vendor2_reg); - - if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) == 0U) { - dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", __func__); - break; - } else { - udelay(1); - } - timeout--; - } - if (timeout == 0U) { - dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); - err = -ETIMEDOUT; - goto fail; - } - } - timeout = 100U; /* Number of iterations */ - while (timeout != 0U) { - mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l0_base, - mphy_rx_vendor2_reg); - - if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) != 0U) { - dev_info(dev, "%s: MPhy Receiver Calibration passed\n", __func__); - break; - } else { - udelay(1); - } - timeout--; - } - if (timeout == 0U) { - dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); - err = -ETIMEDOUT; - goto fail; - } - - /* Clear RX lane calibration */ - mphy_clear_bits(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, - mphy_rx_vendor2_reg); - mphy_update(ufs_tegra->mphy_l0_base, - MPHY_GO_BIT, mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, mphy_rx_vendor2_reg); - if (err) { - dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); + udelay(1); + timeout--; + } + if (timeout == 0U) { + dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); + err = -ETIMEDOUT; goto fail; - } - timeout = 100U; /* Number of iterations */ - while (timeout != 0U) { - mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l0_base, - mphy_rx_vendor2_reg); + } + } + timeout = 100U; /* Number of iterations */ + while (timeout != 0U) { + mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l0_base, + MPHY_RX_APB_VENDOR2_0_T234); - if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) == 0U) { - dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", __func__); - break; - } else { - udelay(1); - } - timeout--; - } - if (timeout == 0U) { - dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); - err = -ETIMEDOUT; - } - } else { - if (ufs_tegra->x2config == true) { - dev_dbg(dev, "%s:x2config is true so invoking mphy_update\n", - __func__); - mphy_update(ufs_tegra->mphy_l1_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, - mphy_rx_vendor2_reg); - } + if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) != 0U) { + dev_info(dev, "%s: MPhy Receiver Calibration passed\n", __func__); + break; + } + udelay(1); + timeout--; + } + if (timeout == 0U) { + dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); + err = -ETIMEDOUT; + goto fail; + } - mphy_update(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, mphy_rx_vendor2_reg); - - if (ufs_tegra->x2config == true) { - /* TODO: GO bit has to be read back after updating it */ - mphy_update(ufs_tegra->mphy_l1_base, - MPHY_GO_BIT, mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, mphy_rx_vendor2_reg); - if (err) { - goto fail; - } - } - - mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, - mphy_rx_vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, mphy_rx_vendor2_reg); - if (err) { - dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); - goto fail; - } - timeout = 10U; /* Number of iterations */ - while (timeout != 0U) { - udelay(1000); - - mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l0_base, - mphy_rx_vendor2_reg); - - if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_EN) == 0U) { - dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", __func__); - break; - } - timeout--; - } - if (timeout == 0U) { - dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); - err = -ETIMEDOUT; - } - } + /* Clear RX lane calibration */ + mphy_clear_bits(ufs_tegra->mphy_l0_base, + MPHY_RX_APB_VENDOR2_0_RX_CAL_EN, + MPHY_RX_APB_VENDOR2_0_T234); + mphy_update(ufs_tegra->mphy_l0_base, + MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) { + dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); + goto fail; + } + timeout = 100U; /* Number of iterations */ + while (timeout != 0U) { + mphy_rx_vendor2 = mphy_readl(ufs_tegra->mphy_l0_base, + MPHY_RX_APB_VENDOR2_0_T234); + if ((mphy_rx_vendor2 & MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE) == 0U) { + dev_dbg(dev, "%s: MPhy Receiver Calibration passed\n", __func__); + break; + } + udelay(1); + timeout--; + } + if (timeout == 0U) { + dev_err(dev, "%s: MPhy Receiver Calibration failed\n", __func__); + err = -ETIMEDOUT; + } fail: - return err; + return err; } static int ufs_tegra_mphy_tx_calibration_enable(struct ufs_tegra_host *ufs_tegra) @@ -371,38 +303,37 @@ static int ufs_tegra_mphy_tx_calibration_enable(struct ufs_tegra_host *ufs_tegra struct device *dev = ufs_tegra->hba->dev; int err = 0; - if ((tegra_sku_info.platform == TEGRA_PLATFORM_VDK) || - (tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA) || - (tegra_sku_info.platform == TEGRA_PLATFORM_VSP) || - (ufs_tegra->soc->chip_id != TEGRA264)) + if (tegra_sku_info.platform == TEGRA_PLATFORM_VDK || + tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA || + tegra_sku_info.platform == TEGRA_PLATFORM_VSP || + ufs_tegra->soc->chip_id != TEGRA264) goto end; /* Enable TX Calibration */ mphy_update(ufs_tegra->mphy_l0_base, - MPHY_TX_APB_VENDOR2_0_TX_CAL_EN, MPHY_TX_APB_TX_VENDOR2_0_T264); - if (ufs_tegra->x2config == true) { + MPHY_TX_APB_VENDOR2_0_TX_CAL_EN, MPHY_TX_APB_TX_VENDOR2_0_T264); + if (ufs_tegra->x2config) { dev_err(dev, "%s:x2config is true so invoking mphy_update\n", - __func__); + __func__); mphy_update(ufs_tegra->mphy_l1_base, - MPHY_TX_APB_VENDOR2_0_TX_CAL_EN, - MPHY_TX_APB_TX_VENDOR2_0_T264); + MPHY_TX_APB_VENDOR2_0_TX_CAL_EN, + MPHY_TX_APB_TX_VENDOR2_0_T264); } mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, - MPHY_TX_APB_TX_VENDOR0_0_T234); + MPHY_TX_APB_TX_VENDOR0_0_T234); err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_TX_APB_TX_VENDOR0_0_T234); if (err) { dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); goto end; } - if (ufs_tegra->x2config == true) { + if (ufs_tegra->x2config) { mphy_update(ufs_tegra->mphy_l1_base, - MPHY_GO_BIT, MPHY_TX_APB_TX_VENDOR0_0_T234); + MPHY_GO_BIT, MPHY_TX_APB_TX_VENDOR0_0_T234); err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_TX_APB_TX_VENDOR0_0_T234); - if (err) { + if (err) dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - } } end: if (err) @@ -411,7 +342,7 @@ end: } static int ufs_tegra_mphy_tx_calibration_status(struct ufs_tegra_host *ufs_tegra, - void __iomem *mphy_base) + void __iomem *mphy_base) { int err = 0; u32 mphy_tx_vendor2; @@ -422,18 +353,17 @@ static int ufs_tegra_mphy_tx_calibration_status(struct ufs_tegra_host *ufs_tegra timeout = 100U; /* Number of iterations */ while (timeout != 0U) { mphy_tx_vendor2 = mphy_readl(mphy_base, - MPHY_TX_APB_TX_VENDOR2_0_T264); + MPHY_TX_APB_TX_VENDOR2_0_T264); if ((mphy_tx_vendor2 & MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE) != 0U) { dev_dbg(dev, "%s: MPhy TX Calibration done\n", __func__); /* Clear TX lane calibration */ - mphy_tx_vendor2 &=~(MPHY_TX_APB_VENDOR2_0_TX_CAL_EN); + mphy_tx_vendor2 &= ~(MPHY_TX_APB_VENDOR2_0_TX_CAL_EN); mphy_writel(mphy_base, mphy_tx_vendor2, MPHY_TX_APB_TX_VENDOR2_0_T264); break; - } else { - udelay(1); } + udelay(1); timeout--; } if (timeout == 0U) { @@ -443,7 +373,7 @@ static int ufs_tegra_mphy_tx_calibration_status(struct ufs_tegra_host *ufs_tegra } mphy_update(mphy_base, MPHY_GO_BIT, - MPHY_TX_APB_TX_VENDOR0_0_T234); + MPHY_TX_APB_TX_VENDOR0_0_T234); err = mphy_go_bit_status(mphy_base, MPHY_TX_APB_TX_VENDOR0_0_T234); if (err) { dev_err(dev, "%s: failed\n", __func__); @@ -454,7 +384,7 @@ static int ufs_tegra_mphy_tx_calibration_status(struct ufs_tegra_host *ufs_tegra timeout = 100U; /* Number of iterations */ while (timeout != 0U) { mphy_tx_vendor2 = mphy_readl(mphy_base, - MPHY_TX_APB_TX_VENDOR2_0_T264); + MPHY_TX_APB_TX_VENDOR2_0_T264); if ((mphy_tx_vendor2 & MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE) == 0U) { dev_dbg(dev, "%s: MPhy TX Calibration clear completed\n", @@ -478,25 +408,25 @@ static int ufs_tegra_mphy_check_tx_calibration_done_status(struct ufs_tegra_host int err = 0; struct device *dev = ufs_tegra->hba->dev; - if ((tegra_sku_info.platform == TEGRA_PLATFORM_VDK) || - (tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA) || - (tegra_sku_info.platform == TEGRA_PLATFORM_VSP) || - (ufs_tegra->soc->chip_id != TEGRA264)) + if (tegra_sku_info.platform == TEGRA_PLATFORM_VDK || + tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA || + tegra_sku_info.platform == TEGRA_PLATFORM_VSP || + ufs_tegra->soc->chip_id != TEGRA264) return 0; - if (ufs_tegra->x2config == true) { + if (ufs_tegra->x2config) { err = ufs_tegra_mphy_tx_calibration_status(ufs_tegra, - ufs_tegra->mphy_l1_base); - if (err ) { - dev_err(dev, "%s: MPhy1 TX Calibration status check failed \n", __func__); + ufs_tegra->mphy_l1_base); + if (err) { + dev_err(dev, "%s: MPhy1 TX Calibration status check failed\n", __func__); goto fail; } } err = ufs_tegra_mphy_tx_calibration_status(ufs_tegra, - ufs_tegra->mphy_l0_base); - if (err ) { - dev_err(dev, "%s: MPhy0 TX Calibration status check failed \n", __func__); + ufs_tegra->mphy_l0_base); + if (err) { + dev_err(dev, "%s: MPhy0 TX Calibration status check failed\n", __func__); goto fail; } dev_info(dev, "%s: MPhy TX Calibration completed\n", __func__); @@ -507,17 +437,17 @@ fail: static void ufs_tegra_mphy_war(struct ufs_tegra_host *ufs_tegra) { - if ((ufs_tegra->soc->chip_id == TEGRA234) && (ufs_tegra->x2config)) { + if (ufs_tegra->soc->chip_id == TEGRA234 && ufs_tegra->x2config) { reset_control_assert(ufs_tegra->mphy_l1_rx_rst); - udelay(50); + ufshcd_delay_us(50, 10); reset_control_deassert(ufs_tegra->mphy_l1_rx_rst); udelay(2); mphy_update(ufs_tegra->mphy_l1_base, - MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, + MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, MPHY_RX_APB_VENDOR3_0_T234); mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, - MPHY_RX_APB_VENDOR2_0_T234); + MPHY_RX_APB_VENDOR2_0_T234); udelay(5); } } @@ -562,19 +492,19 @@ static int ufs_tegra_enable_t234_mphy_clocks(struct ufs_tegra_host *host) if (err) { if (err != -EPROBE_DEFER) dev_err(dev, - "%s mphy_tx_hs_mux_symb_div set parent failed %d\n", - __func__, err); + "%s mphy_tx_hs_mux_symb_div set parent failed %d\n", + __func__, err); goto out; } } err = ufs_tegra_host_clk_enable(dev, "mphy_tx_hs_symb_div", - host->mphy_tx_hs_symb_div); + host->mphy_tx_hs_symb_div); if (err) { if (err != -EPROBE_DEFER) dev_err(dev, - "%s mphy_tx_hs_symb_div clock enable failed %d\n", - __func__, err); + "%s mphy_tx_hs_symb_div clock enable failed %d\n", + __func__, err); goto out; } @@ -590,9 +520,9 @@ static int ufs_tegra_enable_t234_mphy_clocks(struct ufs_tegra_host *host) if (host->soc->chip_id != TEGRA264) { err = clk_set_parent(host->mphy_rx_hs_mux_symb_div, host->mphy_rx_hs_symb_div); if (err) { - dev_err(dev, + dev_err(dev, "%s: mphy_rx_hs_symb_div set parent failed %d\n", - __func__, err); + __func__, err); goto disable_mphy_tx_hs_symb_div; } } @@ -607,7 +537,8 @@ static int ufs_tegra_enable_t234_mphy_clocks(struct ufs_tegra_host *host) } if (host->soc->chip_id != TEGRA264) { - err = ufs_tegra_host_clk_enable(dev, "mphy_l0_tx_2x_symb", host->mphy_l0_tx_2x_symb); + err = ufs_tegra_host_clk_enable(dev, "mphy_l0_tx_2x_symb", + host->mphy_l0_tx_2x_symb); if (err) { if (err != -EPROBE_DEFER) dev_err(dev, @@ -636,60 +567,58 @@ static int ufs_tegra_enable_mphylane_clks(struct ufs_tegra_host *host) if (host->soc->chip_id == TEGRA264) err = ufs_tegra_host_clk_enable(dev, - "mphy_l0_uphy_tx_fifo", - host->mphy_l0_uphy_tx_fifo); + "mphy_l0_uphy_tx_fifo", + host->mphy_l0_uphy_tx_fifo); else err = clk_prepare_enable(host->pllrefe_clk); if (err) goto out; err = ufs_tegra_host_clk_enable(dev, "mphy_core_pll_fixed", - host->mphy_core_pll_fixed); + host->mphy_core_pll_fixed); if (err) goto disable_mphy_clk; err = ufs_tegra_host_clk_enable(dev, "mphy_l0_tx_symb", - host->mphy_l0_tx_symb); + host->mphy_l0_tx_symb); if (err) goto disable_l0_tx_symb; err = ufs_tegra_host_clk_enable(dev, "mphy_tx_1mhz_ref", - host->mphy_tx_1mhz_ref); + host->mphy_tx_1mhz_ref); if (err) goto disable_tx_1mhz_ref; err = ufs_tegra_host_clk_enable(dev, "mphy_l0_rx_ana", - host->mphy_l0_rx_ana); + host->mphy_l0_rx_ana); if (err) goto disable_l0_rx_ana; err = ufs_tegra_host_clk_enable(dev, "mphy_l0_rx_symb", - host->mphy_l0_rx_symb); + host->mphy_l0_rx_symb); if (err) goto disable_l0_rx_symb; err = ufs_tegra_host_clk_enable(dev, "mphy_l0_tx_ls_3xbit", - host->mphy_l0_tx_ls_3xbit); + host->mphy_l0_tx_ls_3xbit); if (err) goto disable_l0_tx_ls_3xbit; err = ufs_tegra_host_clk_enable(dev, "mphy_l0_rx_ls_bit", - host->mphy_l0_rx_ls_bit); + host->mphy_l0_rx_ls_bit); if (err) goto disable_l0_rx_ls_bit; if (host->x2config) { err = ufs_tegra_host_clk_enable(dev, "mphy_l1_rx_ana", - host->mphy_l1_rx_ana); + host->mphy_l1_rx_ana); if (err) goto disable_l1_rx_ana; } - if (host->soc->chip_id >= TEGRA234) { - err = ufs_tegra_enable_t234_mphy_clocks(host); - if (err) - goto disable_t234_clocks; - } + err = ufs_tegra_enable_t234_mphy_clocks(host); + if (err) + goto disable_t234_clocks; host->is_lane_clks_enabled = true; goto out; @@ -725,95 +654,95 @@ static int ufs_tegra_init_mphy_lane_clks(struct ufs_tegra_host *host) int err = 0; struct device *dev = host->hba->dev; - if (host->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_get(dev, - "pllrefe_vcoout", &host->pllrefe_clk); + "pllrefe_vcoout", + &host->pllrefe_clk); if (err) goto out; } else { err = ufs_tegra_host_clk_get(dev, "mphy_l0_uphy_tx_fifo", - &host->mphy_l0_uphy_tx_fifo); + &host->mphy_l0_uphy_tx_fifo); if (err) goto out; } err = ufs_tegra_host_clk_get(dev, - "mphy_core_pll_fixed", &host->mphy_core_pll_fixed); + "mphy_core_pll_fixed", &host->mphy_core_pll_fixed); if (err) goto out; err = ufs_tegra_host_clk_get(dev, - "mphy_l0_tx_symb", &host->mphy_l0_tx_symb); + "mphy_l0_tx_symb", &host->mphy_l0_tx_symb); if (err) goto out; err = ufs_tegra_host_clk_get(dev, "mphy_tx_1mhz_ref", - &host->mphy_tx_1mhz_ref); + &host->mphy_tx_1mhz_ref); if (err) goto out; err = ufs_tegra_host_clk_get(dev, "mphy_l0_rx_ana", - &host->mphy_l0_rx_ana); + &host->mphy_l0_rx_ana); if (err) goto out; err = ufs_tegra_host_clk_get(dev, "mphy_l0_rx_symb", - &host->mphy_l0_rx_symb); + &host->mphy_l0_rx_symb); if (err) goto out; err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_ls_3xbit", - &host->mphy_l0_tx_ls_3xbit); + &host->mphy_l0_tx_ls_3xbit); if (err) goto out; err = ufs_tegra_host_clk_get(dev, "mphy_l0_rx_ls_bit", - &host->mphy_l0_rx_ls_bit); + &host->mphy_l0_rx_ls_bit); if (err) goto out; if (host->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_get(dev, "mphy_force_ls_mode", - &host->mphy_force_ls_mode); + &host->mphy_force_ls_mode); if (err) goto out; } err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_hs_symb_div", - &host->mphy_tx_hs_symb_div); + &host->mphy_tx_hs_symb_div); if (err) goto out; if (host->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_mux_symb_div", - &host->mphy_tx_hs_mux_symb_div); + &host->mphy_tx_hs_mux_symb_div); if (err) goto out; } err = ufs_tegra_host_clk_get(dev, "mphy_l0_rx_hs_symb_div", - &host->mphy_rx_hs_symb_div); + &host->mphy_rx_hs_symb_div); if (err) goto out; if (host->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_get(dev, "mphy_l0_rx_mux_symb_div", - &host->mphy_rx_hs_mux_symb_div); + &host->mphy_rx_hs_mux_symb_div); if (err) goto out; } if (host->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_get(dev, "mphy_l0_tx_2x_symb", - &host->mphy_l0_tx_2x_symb); + &host->mphy_l0_tx_2x_symb); if (err) goto out; } if (host->x2config) { err = ufs_tegra_host_clk_get(dev, "mphy_l1_rx_ana", - &host->mphy_l1_rx_ana); + &host->mphy_l1_rx_ana); if (err) goto out; } @@ -823,7 +752,7 @@ out: } static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra, - bool is_rate_b) + bool is_rate_b) { int err = 0; struct device *dev = ufs_tegra->hba->dev; @@ -833,7 +762,7 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra, return 0; err = ufs_tegra_host_clk_enable(dev, "uphy_pll3", - ufs_tegra->ufs_uphy_pll3); + ufs_tegra->ufs_uphy_pll3); if (err) return err; @@ -845,16 +774,16 @@ static int ufs_tegra_enable_ufs_uphy_pll3(struct ufs_tegra_host *ufs_tegra, rate_b_freq = UFS_CLK_UPHY_PLL3_RATEB; err = clk_set_rate(ufs_tegra->ufs_uphy_pll3, - rate_b_freq); + rate_b_freq); } } else { if (ufs_tegra->ufs_uphy_pll3) err = clk_set_rate(ufs_tegra->ufs_uphy_pll3, - UFS_CLK_UPHY_PLL3_RATEA); + UFS_CLK_UPHY_PLL3_RATEA); } if (err) dev_err(dev, "%s: failed to set ufs_uphy_pll3 freq err %d", - __func__, err); + __func__, err); return err; } @@ -867,7 +796,7 @@ static int ufs_tegra_init_uphy_pll3(struct ufs_tegra_host *ufs_tegra) return 0; err = ufs_tegra_host_clk_get(dev, - "uphy_pll3", &ufs_tegra->ufs_uphy_pll3); + "uphy_pll3", &ufs_tegra->ufs_uphy_pll3); return err; } @@ -877,7 +806,7 @@ static int ufs_tegra_init_ufs_clks(struct ufs_tegra_host *ufs_tegra) struct device *dev = ufs_tegra->hba->dev; err = ufs_tegra_host_clk_get(dev, - "ufshc", &ufs_tegra->ufshc_clk); + "ufshc", &ufs_tegra->ufshc_clk); if (err) goto out; @@ -885,21 +814,21 @@ static int ufs_tegra_init_ufs_clks(struct ufs_tegra_host *ufs_tegra) goto out; if (ufs_tegra->soc->chip_id != TEGRA264) { - err = ufs_tegra_host_clk_get(dev, - "pll_p", &ufs_tegra->ufshc_parent); + err = ufs_tegra_host_clk_get(dev, "pll_p", + &ufs_tegra->ufshc_parent); if (err) goto out; } else { - err = ufs_tegra_host_clk_get(dev, - "pllrefe_vcoout", &ufs_tegra->ufshc_parent); + err = ufs_tegra_host_clk_get(dev, "pllrefe_vcoout", + &ufs_tegra->ufshc_parent); if (err) { dev_err(dev, "%s: pllrefe_vcoout clock get failed: Err %d", __func__, err); goto out; } - err = ufs_tegra_host_clk_get(dev, - "ufshc_div", &ufs_tegra->ufshc_clk_div); + err = ufs_tegra_host_clk_get(dev, "ufshc_div", + &ufs_tegra->ufshc_clk_div); if (err) { dev_err(dev, "%s: ufshc_div clock get failed: Err %d", __func__, err); @@ -907,15 +836,15 @@ static int ufs_tegra_init_ufs_clks(struct ufs_tegra_host *ufs_tegra) } err = ufs_tegra_host_clk_get(dev, - "isc_cpu", &ufs_tegra->isc_cpu); + "isc_cpu", &ufs_tegra->isc_cpu); if (err) { dev_err(dev, "%s: isc_cpu clock get failed: Err %d", __func__, err); goto out; } - err = ufs_tegra_host_clk_get(dev, - "utmi_pll1", &ufs_tegra->utmi_pll1); + err = ufs_tegra_host_clk_get(dev, "utmi_pll1", + &ufs_tegra->utmi_pll1); if (err) { dev_err(dev, "%s: utmi_pll1 clock get failed: Err %d", __func__, err); @@ -924,19 +853,19 @@ static int ufs_tegra_init_ufs_clks(struct ufs_tegra_host *ufs_tegra) } if (ufs_tegra->soc->chip_id != TEGRA264) { - err = ufs_tegra_host_clk_get(dev, - "clk_m", &ufs_tegra->ufsdev_parent); + err = ufs_tegra_host_clk_get(dev, "clk_m", + &ufs_tegra->ufsdev_parent); if (err) goto out; } err = ufs_tegra_host_clk_get(dev, - "ufsdev_ref", &ufs_tegra->ufsdev_ref_clk); + "ufsdev_ref", &ufs_tegra->ufsdev_ref_clk); if (err) goto out; err = ufs_tegra_host_clk_get(dev, - "osc", &ufs_tegra->ufsdev_osc); + "osc", &ufs_tegra->ufsdev_osc); out: return err; @@ -949,7 +878,7 @@ static int ufs_tegra_enable_ufs_clks(struct ufs_tegra_host *ufs_tegra) if (tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA) { err = ufs_tegra_host_clk_enable(dev, "ufshc", - ufs_tegra->ufshc_clk); + ufs_tegra->ufshc_clk); goto out; } @@ -958,18 +887,18 @@ static int ufs_tegra_enable_ufs_clks(struct ufs_tegra_host *ufs_tegra) * for ufs */ err = clk_set_parent(ufs_tegra->ufshc_clk, - ufs_tegra->ufshc_clk_div); + ufs_tegra->ufshc_clk_div); if (err) { pr_err("\n ufshc_clk clk_set_parent failed\n"); goto out; } err = clk_set_parent(ufs_tegra->isc_cpu, - ufs_tegra->utmi_pll1); + ufs_tegra->utmi_pll1); } else { err = clk_set_parent(ufs_tegra->ufshc_clk, - ufs_tegra->ufshc_parent); + ufs_tegra->ufshc_parent); } if (err) { pr_err("\n clk_set_parent failed\n"); @@ -989,7 +918,7 @@ static int ufs_tegra_enable_ufs_clks(struct ufs_tegra_host *ufs_tegra) } err = ufs_tegra_host_clk_enable(dev, "ufshc", - ufs_tegra->ufshc_clk); + ufs_tegra->ufshc_clk); if (err) { pr_err("ufshc clock enable failed %d\n", err); @@ -1000,14 +929,13 @@ static int ufs_tegra_enable_ufs_clks(struct ufs_tegra_host *ufs_tegra) * Frequency is 19.2 MHz. */ err = ufs_tegra_host_clk_enable(dev, "ufsdev_ref", - ufs_tegra->ufsdev_ref_clk); + ufs_tegra->ufsdev_ref_clk); if (err) goto disable_ufshc; - if ((ufs_tegra->soc->chip_id >= TEGRA234) && - (ufs_tegra->enable_38mhz_clk)) { + if (ufs_tegra->enable_38mhz_clk) { err = clk_set_parent(ufs_tegra->ufsdev_ref_clk, - ufs_tegra->ufsdev_osc); + ufs_tegra->ufsdev_osc); if (err) { pr_err("Function clk_set_parent failed\n"); @@ -1075,7 +1003,7 @@ static void ufs_tegra_ufs_deassert_reset(struct ufs_tegra_host *ufs_tegra) reset_control_assert(ufs_tegra->ufs_rst); reset_control_assert(ufs_tegra->ufs_axi_m_rst); reset_control_assert(ufs_tegra->ufshc_lp_rst); - udelay(100); + ufshcd_delay_us(100, 10); reset_control_deassert(ufs_tegra->ufs_rst); reset_control_deassert(ufs_tegra->ufs_axi_m_rst); @@ -1120,7 +1048,7 @@ static int ufs_tegra_mphy_reset_init(struct ufs_tegra_host *ufs_tegra) if (IS_ERR(ufs_tegra->mphy_l1_rx_rst)) { ret = PTR_ERR(ufs_tegra->mphy_l1_rx_rst); dev_err(dev, - "Reset control for mphy-l1-rx-rst not found: %d\n", + "Reset control for mphy-l1-rx-rst not found: %d\n", ret); } @@ -1129,7 +1057,7 @@ static int ufs_tegra_mphy_reset_init(struct ufs_tegra_host *ufs_tegra) if (IS_ERR(ufs_tegra->mphy_l1_tx_rst)) { ret = PTR_ERR(ufs_tegra->mphy_l1_tx_rst); dev_err(dev, - "Reset control for mphy_l1_tx_rst not found: %d\n", + "Reset control for mphy_l1_tx_rst not found: %d\n", ret); } } @@ -1161,19 +1089,13 @@ static void ufs_tegra_mphy_deassert_reset(struct ufs_tegra_host *ufs_tegra) static int ufs_tegra_pwr_change_clk_boost(struct ufs_tegra_host *ufs_tegra) { - u32 reg_vendor_0; struct device *dev = ufs_tegra->hba->dev; int err; - if (ufs_tegra->soc->chip_id >= TEGRA234) - reg_vendor_0 = MPHY_RX_APB_VENDOR2_0_T234; - else - reg_vendor_0 = MPHY_RX_APB_VENDOR2_0; - mphy_writel(ufs_tegra->mphy_l0_base, MPHY_PWR_CHANGE_CLK_BOOST, - MPHY_RX_APB_VENDOR49_0_T234); - mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, reg_vendor_0); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, reg_vendor_0); + MPHY_RX_APB_VENDOR49_0_T234); + mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); if (err) { dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); goto end; @@ -1181,16 +1103,15 @@ static int ufs_tegra_pwr_change_clk_boost(struct ufs_tegra_host *ufs_tegra) if (ufs_tegra->x2config) { mphy_writel(ufs_tegra->mphy_l1_base, MPHY_PWR_CHANGE_CLK_BOOST, - MPHY_RX_APB_VENDOR49_0_T234); - mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, reg_vendor_0); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, reg_vendor_0); - if (err) { - dev_err(dev, "%s: Go bit clear failed for for mphy1\n", __func__); + MPHY_RX_APB_VENDOR49_0_T234); + mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) { + dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); goto end; - } - + } } - udelay(20); + ufshcd_delay_us(20, 10); end: return err; } @@ -1201,29 +1122,20 @@ static int ufs_tegra_mphy_rx_sync_capability(struct ufs_tegra_host *ufs_tegra) u32 val_94_97 = 0; u32 val_8c_8f = 0; u32 val_98_9b = 0; - u32 vendor2_reg, vendor3_reg; struct device *dev = ufs_tegra->hba->dev; int err = 0; - if (ufs_tegra->soc->chip_id >= TEGRA234) { - vendor2_reg = MPHY_RX_APB_VENDOR2_0_T234; - vendor3_reg = MPHY_RX_APB_VENDOR3_0_T234; - } else { - vendor2_reg = MPHY_RX_APB_VENDOR2_0; - vendor3_reg = MPHY_RX_APB_VENDOR3_0; - } - /* MPHY RX sync lengths capability changes */ /*Update HS_G1 Sync Length MPHY_RX_APB_CAPABILITY_88_8B_0*/ val_88_8b = mphy_readl(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_CAPABILITY_88_8B_0); + MPHY_RX_APB_CAPABILITY_88_8B_0); val_88_8b &= ~RX_HS_G1_SYNC_LENGTH_CAPABILITY(~0); val_88_8b |= RX_HS_G1_SYNC_LENGTH_CAPABILITY(RX_HS_SYNC_LENGTH); /*Update HS_G2&G3 Sync Length MPHY_RX_APB_CAPABILITY_94_97_0*/ val_94_97 = mphy_readl(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_CAPABILITY_94_97_0); + MPHY_RX_APB_CAPABILITY_94_97_0); val_94_97 &= ~RX_HS_G2_SYNC_LENGTH_CAPABILITY(~0); val_94_97 |= RX_HS_G2_SYNC_LENGTH_CAPABILITY(RX_HS_SYNC_LENGTH); val_94_97 &= ~RX_HS_G3_SYNC_LENGTH_CAPABILITY(~0); @@ -1233,32 +1145,31 @@ static int ufs_tegra_mphy_rx_sync_capability(struct ufs_tegra_host *ufs_tegra) /* Update MPHY_RX_APB_CAPABILITY_8C_8F_0 */ val_8c_8f = mphy_readl(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_CAPABILITY_8C_8F_0); + MPHY_RX_APB_CAPABILITY_8C_8F_0); val_8c_8f &= ~RX_MIN_ACTIVATETIME_CAP_ARG(~0); val_8c_8f |= RX_MIN_ACTIVATETIME_CAP_ARG(RX_MIN_ACTIVATETIME); /* Update MPHY_RX_APB_CAPABILITY_98_9B_0 */ val_98_9b = mphy_readl(ufs_tegra->mphy_l0_base, - MPHY_RX_APB_CAPABILITY_98_9B_0); + MPHY_RX_APB_CAPABILITY_98_9B_0); val_98_9b &= ~RX_ADVANCED_FINE_GRANULARITY(~0); val_98_9b &= ~RX_ADVANCED_GRANULARITY(~0); val_98_9b &= ~RX_ADVANCED_MIN_ACTIVATETIME(~0); val_98_9b |= RX_ADVANCED_MIN_ACTIVATETIME(RX_ADVANCED_MIN_AT); mphy_writel(ufs_tegra->mphy_l0_base, val_88_8b, - MPHY_RX_APB_CAPABILITY_88_8B_0); + MPHY_RX_APB_CAPABILITY_88_8B_0); mphy_writel(ufs_tegra->mphy_l0_base, val_94_97, - MPHY_RX_APB_CAPABILITY_94_97_0); + MPHY_RX_APB_CAPABILITY_94_97_0); mphy_writel(ufs_tegra->mphy_l0_base, val_8c_8f, - MPHY_RX_APB_CAPABILITY_8C_8F_0); + MPHY_RX_APB_CAPABILITY_8C_8F_0); mphy_writel(ufs_tegra->mphy_l0_base, val_98_9b, - MPHY_RX_APB_CAPABILITY_98_9B_0); + MPHY_RX_APB_CAPABILITY_98_9B_0); mphy_update(ufs_tegra->mphy_l0_base, - MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, - vendor3_reg); - mphy_update(ufs_tegra->mphy_l0_base, - MPHY_GO_BIT, vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, vendor2_reg); + MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, + MPHY_RX_APB_VENDOR3_0_T234); + mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); if (err) { dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); goto fail; @@ -1266,23 +1177,22 @@ static int ufs_tegra_mphy_rx_sync_capability(struct ufs_tegra_host *ufs_tegra) if (ufs_tegra->x2config) { mphy_writel(ufs_tegra->mphy_l1_base, val_88_8b, - MPHY_RX_APB_CAPABILITY_88_8B_0); + MPHY_RX_APB_CAPABILITY_88_8B_0); mphy_writel(ufs_tegra->mphy_l1_base, val_94_97, - MPHY_RX_APB_CAPABILITY_94_97_0); + MPHY_RX_APB_CAPABILITY_94_97_0); mphy_writel(ufs_tegra->mphy_l1_base, val_8c_8f, - MPHY_RX_APB_CAPABILITY_8C_8F_0); + MPHY_RX_APB_CAPABILITY_8C_8F_0); mphy_writel(ufs_tegra->mphy_l1_base, val_98_9b, - MPHY_RX_APB_CAPABILITY_98_9B_0); + MPHY_RX_APB_CAPABILITY_98_9B_0); mphy_update(ufs_tegra->mphy_l1_base, - MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, - vendor3_reg); + MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL, + MPHY_RX_APB_VENDOR3_0_T234); /* set gobit */ mphy_update(ufs_tegra->mphy_l1_base, - MPHY_GO_BIT, vendor2_reg); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, vendor2_reg); - if (err) { + MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - } } fail: return err; @@ -1290,15 +1200,10 @@ fail: static int ufs_tegra_mphy_rx_advgran(struct ufs_tegra_host *ufs_tegra) { - u32 val = 0, reg_vendor_2; - struct device *dev = ufs_tegra->hba->dev; + u32 val = 0; + struct device *dev = ufs_tegra->hba->dev; int err; - if (ufs_tegra->soc->chip_id >= TEGRA234) - reg_vendor_2 = MPHY_RX_APB_VENDOR2_0_T234; - else - reg_vendor_2 = MPHY_RX_APB_VENDOR2_0; - val = mphy_readl(ufs_tegra->mphy_l0_base, MPHY_RX_APB_CAPABILITY_98_9B_0); val &= ~RX_ADVANCED_GRANULARITY(~0); val |= RX_ADVANCED_GRANULARITY(0x1); @@ -1307,10 +1212,10 @@ static int ufs_tegra_mphy_rx_advgran(struct ufs_tegra_host *ufs_tegra) val |= RX_ADVANCED_MIN_ACTIVATETIME(0x8); mphy_writel(ufs_tegra->mphy_l0_base, val, - MPHY_RX_APB_CAPABILITY_98_9B_0); + MPHY_RX_APB_CAPABILITY_98_9B_0); mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, - reg_vendor_2); - err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, reg_vendor_2); + MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); if (err) { dev_err(dev, "%s: Go bit clear failed for mphy0\n", __func__); goto end; @@ -1318,7 +1223,7 @@ static int ufs_tegra_mphy_rx_advgran(struct ufs_tegra_host *ufs_tegra) if (ufs_tegra->x2config) { val = mphy_readl(ufs_tegra->mphy_l1_base, - MPHY_RX_APB_CAPABILITY_98_9B_0); + MPHY_RX_APB_CAPABILITY_98_9B_0); val &= ~RX_ADVANCED_GRANULARITY(~0); val |= RX_ADVANCED_GRANULARITY(0x1); @@ -1326,13 +1231,11 @@ static int ufs_tegra_mphy_rx_advgran(struct ufs_tegra_host *ufs_tegra) val |= RX_ADVANCED_MIN_ACTIVATETIME(0x8); mphy_writel(ufs_tegra->mphy_l1_base, val, - MPHY_RX_APB_CAPABILITY_98_9B_0); - mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, - reg_vendor_2); - err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, reg_vendor_2); - if (err) { + MPHY_RX_APB_CAPABILITY_98_9B_0); + mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); + err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); + if (err) dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - } } end: return err; @@ -1341,33 +1244,30 @@ end: static void ufs_tegra_ufs_aux_ref_clk_enable(struct ufs_tegra_host *ufs_tegra) { ufs_aux_update(ufs_tegra->ufs_aux_base, UFSHC_DEV_CLK_EN, - UFSHC_AUX_UFSHC_DEV_CTRL_0); + UFSHC_AUX_UFSHC_DEV_CTRL_0); } static void ufs_tegra_ufs_aux_ref_clk_disable(struct ufs_tegra_host *ufs_tegra) { ufs_aux_clear_bits(ufs_tegra->ufs_aux_base, UFSHC_DEV_CLK_EN, - UFSHC_AUX_UFSHC_DEV_CTRL_0); + UFSHC_AUX_UFSHC_DEV_CTRL_0); } static void ufs_tegra_aux_reset_enable(struct ufs_tegra_host *ufs_tegra) { ufs_aux_clear_bits(ufs_tegra->ufs_aux_base, - UFSHC_DEV_RESET, - UFSHC_AUX_UFSHC_DEV_CTRL_0); + UFSHC_DEV_RESET, UFSHC_AUX_UFSHC_DEV_CTRL_0); } static void ufs_tegra_ufs_aux_prog(struct ufs_tegra_host *ufs_tegra) { - /* * Release the reset to UFS device on pin ufs_rst_n */ if (ufs_tegra->ufshc_state != UFSHC_SUSPEND) ufs_aux_update(ufs_tegra->ufs_aux_base, UFSHC_DEV_RESET, - UFSHC_AUX_UFSHC_DEV_CTRL_0); - + UFSHC_AUX_UFSHC_DEV_CTRL_0); if (ufs_tegra->ufshc_state == UFSHC_SUSPEND) { /* @@ -1383,154 +1283,30 @@ static void ufs_tegra_ufs_aux_prog(struct ufs_tegra_host *ufs_tegra) } } -static void ufs_tegra_context_save(struct ufs_tegra_host *ufs_tegra) -{ - u32 reg_len = 0; - u32 len = 0; - u32 *mphy_context_save = ufs_tegra->mphy_context; - - reg_len = ARRAY_SIZE(mphy_rx_apb); - /* - * Save mphy_rx_apb lane0 and lane1 context - */ - ufs_save_regs(ufs_tegra->mphy_l0_base, mphy_context_save, - mphy_rx_apb, reg_len); - len += reg_len; - - if (ufs_tegra->x2config) { - ufs_save_regs(ufs_tegra->mphy_l1_base, mphy_context_save + len, - mphy_rx_apb, reg_len); - len += reg_len; - } - - reg_len = ARRAY_SIZE(mphy_tx_apb); - /* - * Save mphy_tx_apb lane0 and lane1 context - */ - ufs_save_regs(ufs_tegra->mphy_l0_base, mphy_context_save + len, - mphy_tx_apb, reg_len); - len += reg_len; - if (ufs_tegra->x2config) - ufs_save_regs(ufs_tegra->mphy_l1_base, - mphy_context_save + len, mphy_tx_apb, reg_len); -} - -static void ufs_tegra_context_restore(struct ufs_tegra_host *ufs_tegra) -{ - u32 reg_len = 0; - u32 len = 0; - u32 *mphy_context_restore = ufs_tegra->mphy_context; - u32 reg_vendor_0, reg_vendor_2; - - if (ufs_tegra->soc->chip_id >= TEGRA234) { - reg_vendor_0 = MPHY_TX_APB_TX_VENDOR0_0_T234; - reg_vendor_2 = MPHY_RX_APB_VENDOR2_0_T234; - } else { - reg_vendor_0 = MPHY_TX_APB_TX_VENDOR0_0; - reg_vendor_2 = MPHY_RX_APB_VENDOR2_0; - } - - reg_len = ARRAY_SIZE(mphy_rx_apb); - /* - * Restore mphy_rx_apb lane0 and lane1 context - */ - ufs_restore_regs(ufs_tegra->mphy_l0_base, mphy_context_restore, - mphy_rx_apb, reg_len); - mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, reg_vendor_2); - - len += reg_len; - if (ufs_tegra->x2config) { - ufs_restore_regs(ufs_tegra->mphy_l1_base, - mphy_context_restore + len, mphy_rx_apb, reg_len); - mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, - reg_vendor_2); - len += reg_len; - } - - reg_len = ARRAY_SIZE(mphy_tx_apb); - /* - * Restore mphy_tx_apb lane0 and lane1 context - */ - ufs_restore_regs(ufs_tegra->mphy_l0_base, mphy_context_restore + len, - mphy_tx_apb, reg_len); - mphy_writel(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, reg_vendor_0); - - len += reg_len; - if (ufs_tegra->x2config) { - ufs_restore_regs(ufs_tegra->mphy_l1_base, - mphy_context_restore + len, mphy_tx_apb, reg_len); - mphy_writel(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, reg_vendor_0); - } -} - #if defined(NV_UFS_HBA_VARIANT_OPS_SUSPEND_HAS_STATUS_ARG) static int ufs_tegra_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, - enum ufs_notify_change_status status) + enum ufs_notify_change_status status) #else static int ufs_tegra_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) #endif { struct ufs_tegra_host *ufs_tegra = hba->priv; - struct device *dev = hba->dev; - u32 val; int ret = 0; - int timeout = 500; - bool is_ufs_lp_pwr_gated = false; if (pm_op != UFS_SYSTEM_PM) return 0; ufs_tegra->ufshc_state = UFSHC_SUSPEND; - if (ufs_tegra->soc->chip_id < TEGRA234) { - /* - * Enable DPD for UFS - */ - if (ufs_tegra->ufs_pinctrl && - !IS_ERR_OR_NULL(ufs_tegra->dpd_enable)) { - ret = pinctrl_select_state(ufs_tegra->ufs_pinctrl, - ufs_tegra->dpd_enable); - if (ret) - dev_err(dev, "pinctrl power down fail %d\n", - ret); - } - - do { - udelay(100); - val = ufs_aux_readl(ufs_tegra->ufs_aux_base, - UFSHC_AUX_UFSHC_STATUS_0); - if (val & UFSHC_HIBERNATE_STATUS) { - is_ufs_lp_pwr_gated = true; - break; - } - timeout--; - } while (timeout > 0); - - if (timeout <= 0) { - dev_err(dev, "UFSHC_AUX_UFSHC_STATUS_0 = %x\n", val); - return -ETIMEDOUT; - } - - if (is_ufs_lp_pwr_gated) { - /* - * Save all armphy_rx_apb and armphy_tx_apb registers - * T234 does not require context save - */ - ufs_tegra_context_save(ufs_tegra); - reset_control_assert(ufs_tegra->ufshc_lp_rst); - } - } else { - /* - * For T234, during sc7 entry, the link is set to off state - * so that during sc7 exit link startup happens (According to IAS) - */ - ufshcd_set_link_off(hba); - } + /* + * For T234, during sc7 entry, the link is set to off state + * so that during sc7 exit link startup happens (According to IAS) + */ + ufshcd_set_link_off(hba); /* TODO: Check why disabling clocks causing crash */ - if (ufs_tegra->soc->chip_id == TEGRA264) { + if (ufs_tegra->soc->chip_id == TEGRA264) goto end; - } /* Clocks are not present on VDK */ if (tegra_sku_info.platform == TEGRA_PLATFORM_VDK) @@ -1560,7 +1336,6 @@ end: return ret; } - static int ufs_tegra_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) { struct ufs_tegra_host *ufs_tegra = hba->priv; @@ -1588,29 +1363,13 @@ deassert_ufs_clk: ufs_tegra_ufs_deassert_reset(ufs_tegra); ufs_tegra_ufs_aux_prog(ufs_tegra); - if (ufs_tegra->soc->chip_id < TEGRA234) { - if (ufs_tegra->ufs_pinctrl && - !IS_ERR_OR_NULL(ufs_tegra->dpd_disable)) { - ret = pinctrl_select_state(ufs_tegra->ufs_pinctrl, - ufs_tegra->dpd_disable); - if (ret) { - dev_err(dev, "pinctrl power up fail %d\n", ret); - goto out_disable_mphylane_clks; - } - } - /* - * T234 does not require context restore - */ - ufs_tegra_context_restore(ufs_tegra); - } else { - if (dev_iommu_fwspec_get(dev) != NULL) { - writel(UFS_AUX_ADDR_VIRT_CTRL_EN, - ufs_tegra->ufs_virtualization_base + - UFS_AUX_ADDR_VIRT_CTRL_0); - writel(ufs_tegra->streamid, - ufs_tegra->ufs_virtualization_base + - UFS_AUX_ADDR_VIRT_REG_0); - } + if (dev_iommu_fwspec_get(dev)) { + writel(UFS_AUX_ADDR_VIRT_CTRL_EN, + ufs_tegra->ufs_virtualization_base + + UFS_AUX_ADDR_VIRT_CTRL_0); + writel(ufs_tegra->streamid, + ufs_tegra->ufs_virtualization_base + + UFS_AUX_ADDR_VIRT_REG_0); } if (tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA) @@ -1625,7 +1384,6 @@ end: return ret; -out_disable_mphylane_clks: ufs_tegra_disable_mphylane_clks(ufs_tegra); out_disable_ufs_clks: ufs_tegra_disable_ufs_clks(ufs_tegra); @@ -1634,7 +1392,7 @@ out_disable_ufs_clks: } static void ufs_tegra_print_power_mode_config(struct ufs_hba *hba, - struct ufs_pa_layer_attr *configured_params) + struct ufs_pa_layer_attr *configured_params) { u32 rx_gear; u32 tx_gear; @@ -1649,11 +1407,11 @@ static void ufs_tegra_print_power_mode_config(struct ufs_hba *hba, else if (configured_params->hs_rate == PA_HS_MODE_B) freq_series = "RATE_B"; dev_info(hba->dev, - "HS Mode RX_Gear:gear_%u TX_Gear:gear_%u %s series\n", + "HS Mode RX_Gear:gear_%u TX_Gear:gear_%u %s series\n", rx_gear, tx_gear, freq_series); } else { dev_info(hba->dev, - "PWM Mode RX_Gear:gear_%u TX_Gear:gear_%u\n", + "PWM Mode RX_Gear:gear_%u TX_Gear:gear_%u\n", rx_gear, tx_gear); } } @@ -1697,7 +1455,7 @@ static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, case PRE_CHANGE: /* Update VS_DebugSaveConfigTime Tref */ ufshcd_dme_get(hba, UIC_ARG_MIB(VS_DEBUGSAVECONFIGTIME), - &vs_save_config); + &vs_save_config); /* Update VS_DebugSaveConfigTime st_sct */ vs_save_config &= ~SET_ST_SCT(~0); vs_save_config |= SET_ST_SCT(VS_DEBUGSAVECONFIGTIME_ST_SCT); @@ -1706,12 +1464,12 @@ static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, vs_save_config |= SET_TREF(VS_DEBUGSAVECONFIGTIME_TREF); ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGSAVECONFIGTIME), - vs_save_config); + vs_save_config); memcpy(dev_req_params, dev_max_params, - sizeof(struct ufs_pa_layer_attr)); + sizeof(struct ufs_pa_layer_attr)); - if ((ufs_tegra->enable_hs_mode) && (dev_max_params->hs_rate)) { + if (ufs_tegra->enable_hs_mode && dev_max_params->hs_rate) { if (ufs_tegra->max_hs_gear) { if (dev_max_params->gear_rx > ufs_tegra->max_hs_gear) @@ -1735,7 +1493,7 @@ static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, if (ufs_tegra->mask_hs_mode_b) { dev_req_params->hs_rate = PA_HS_MODE_A; ufs_tegra_enable_ufs_uphy_pll3(ufs_tegra, - false); + false); } else { ufs_tegra_enable_ufs_uphy_pll3(ufs_tegra, true); } @@ -1751,15 +1509,15 @@ static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, if (ret) goto out; ufshcd_dme_configure_adapt(hba, dev_req_params->gear_rx, - PA_INITIAL_ADAPT); + PA_INITIAL_ADAPT); } } else { if (ufs_tegra->max_pwm_gear) { ufshcd_dme_get(hba, - UIC_ARG_MIB(PA_MAXRXPWMGEAR), + UIC_ARG_MIB(PA_MAXRXPWMGEAR), &dev_req_params->gear_rx); ufshcd_dme_peer_get(hba, - UIC_ARG_MIB(PA_MAXRXPWMGEAR), + UIC_ARG_MIB(PA_MAXRXPWMGEAR), &dev_req_params->gear_tx); if (dev_req_params->gear_rx > ufs_tegra->max_pwm_gear) @@ -1778,7 +1536,7 @@ static int ufs_tegra_pwr_change_notify(struct ufs_hba *hba, dev_req_params->hs_rate = 0; } memcpy(&hba->max_pwr_info.info, dev_req_params, - sizeof(struct ufs_pa_layer_attr)); + sizeof(struct ufs_pa_layer_attr)); break; case POST_CHANGE: ufs_tegra_print_power_mode_config(hba, dev_req_params); @@ -1794,7 +1552,7 @@ out: } static int ufs_tegra_hce_enable_notify(struct ufs_hba *hba, - enum ufs_notify_change_status status) + enum ufs_notify_change_status status) { struct ufs_tegra_host *ufs_tegra = hba->priv; struct device *dev = ufs_tegra->hba->dev; @@ -1804,30 +1562,29 @@ static int ufs_tegra_hce_enable_notify(struct ufs_hba *hba, case PRE_CHANGE: if (ufs_tegra->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_enable(dev, - "mphy_force_ls_mode", - ufs_tegra->mphy_force_ls_mode); + "mphy_force_ls_mode", + ufs_tegra->mphy_force_ls_mode); if (err) return err; } - udelay(500); + ufshcd_delay_us(500, 10); ufs_aux_clear_bits(ufs_tegra->ufs_aux_base, - UFSHC_DEV_RESET, - UFSHC_AUX_UFSHC_DEV_CTRL_0); + UFSHC_DEV_RESET, + UFSHC_AUX_UFSHC_DEV_CTRL_0); break; case POST_CHANGE: ufs_aux_clear_bits(ufs_tegra->ufs_aux_base, - UFSHC_CG_SYS_CLK_OVR_ON, - UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0); + UFSHC_CG_SYS_CLK_OVR_ON, + UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0); ufs_tegra_ufs_aux_prog(ufs_tegra); ufs_tegra_set_clk_div(hba); if (ufs_tegra->soc->chip_id != TEGRA264) clk_disable_unprepare(ufs_tegra->mphy_force_ls_mode); - if (ufs_tegra->soc->chip_id >= TEGRA234) - ufs_tegra_ufs_mmio_axi(hba); + ufs_tegra_ufs_mmio_axi(hba); /* Enable auto hibernate */ if (ufs_tegra->enable_auto_hibern8) ufs_aux_writel(ufs_tegra->ufs_aux_base, 0x4, - UFSHC_AUX_UFSHC_CARD_DET_LP_PWR_CTRL_0); + UFSHC_AUX_UFSHC_CARD_DET_LP_PWR_CTRL_0); break; default: break; @@ -1861,8 +1618,7 @@ static void ufs_tegra_unipro_post_linkup(struct ufs_hba *hba) * burst closure delay needs to be configured. */ ufshcd_dme_set(hba, UIC_ARG_MIB(VS_TXBURSTCLOSUREDELAY), - ufs_tegra->vs_burst); - + ufs_tegra->vs_burst); } static void ufs_tegra_unipro_pre_linkup(struct ufs_hba *hba) @@ -1874,26 +1630,22 @@ static void ufs_tegra_unipro_pre_linkup(struct ufs_hba *hba) * burst closure delay needs to be configured to 0[7:0] */ ufshcd_dme_get(hba, UIC_ARG_MIB(VS_TXBURSTCLOSUREDELAY), - &ufs_tegra->vs_burst); + &ufs_tegra->vs_burst); ufshcd_dme_set(hba, UIC_ARG_MIB(VS_TXBURSTCLOSUREDELAY), 0x0); } static int ufs_tegra_link_startup_notify(struct ufs_hba *hba, - enum ufs_notify_change_status status) + enum ufs_notify_change_status status) { struct ufs_tegra_host *ufs_tegra = hba->priv; int err = 0; switch (status) { case PRE_CHANGE: - if (tegra_sku_info.platform == TEGRA_PLATFORM_SYSTEM_FPGA) { - ufs_tegra_mphy_startup_sequence(ufs_tegra); - } else { - ufs_tegra_mphy_rx_sync_capability(ufs_tegra); - ufs_tegra_unipro_pre_linkup(hba); - /* Enable TX link calibration */ - err = ufs_tegra_mphy_tx_calibration_enable(ufs_tegra); - } + ufs_tegra_mphy_rx_sync_capability(ufs_tegra); + ufs_tegra_unipro_pre_linkup(hba); + /* Enable TX link calibration */ + err = ufs_tegra_mphy_tx_calibration_enable(ufs_tegra); break; case POST_CHANGE: /* Check TX link calibration status */ @@ -1905,7 +1657,7 @@ static int ufs_tegra_link_startup_notify(struct ufs_hba *hba, ufs_tegra_unipro_post_linkup(hba); err = ufs_tegra_mphy_receiver_calibration(ufs_tegra, - ufs_tegra->mphy_l0_base); + ufs_tegra->mphy_l0_base); if (err) return err; ufs_tegra_mphy_war(ufs_tegra); @@ -1922,9 +1674,6 @@ static int ufs_tegra_config_soc_data(struct ufs_tegra_host *ufs_tegra) struct device *dev = ufs_tegra->hba->dev; struct device_node *np = dev->of_node; - ufs_tegra->enable_mphy_rx_calib = - of_property_read_bool(np, "nvidia,enable-rx-calib"); - ufs_tegra->x2config = of_property_read_bool(np, "nvidia,enable-x2-config"); @@ -1946,10 +1695,9 @@ static int ufs_tegra_config_soc_data(struct ufs_tegra_host *ufs_tegra) ufs_tegra->configure_uphy_pll3 = of_property_read_bool(np, "nvidia,configure-uphy-pll3"); - of_property_read_u32(np, "nvidia,max-hs-gear", &ufs_tegra->max_hs_gear); of_property_read_u32(np, "nvidia,max-pwm-gear", - &ufs_tegra->max_pwm_gear); + &ufs_tegra->max_pwm_gear); ufs_tegra->enable_scramble = of_property_read_bool(np, "nvidia,enable-scramble"); @@ -1962,7 +1710,7 @@ static int ufs_tegra_config_soc_data(struct ufs_tegra_host *ufs_tegra) ufs_tegra->hba->quirks |= UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS; #else dev_err(dev, "UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS not supported!\n"); - return -ENOTSUPP; + return -EOPNOTSUPP; #endif } #endif @@ -1976,7 +1724,7 @@ static int ufs_tegra_eq_timeout(struct ufs_tegra_host *ufs_tegra) int err; mphy_writel(ufs_tegra->mphy_l0_base, MPHY_EQ_TIMEOUT, - MPHY_RX_APB_VENDOR3B_0_T234); + MPHY_RX_APB_VENDOR3B_0_T234); mphy_update(ufs_tegra->mphy_l0_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); err = mphy_go_bit_status(ufs_tegra->mphy_l0_base, MPHY_RX_APB_VENDOR2_0_T234); if (err) { @@ -1985,216 +1733,15 @@ static int ufs_tegra_eq_timeout(struct ufs_tegra_host *ufs_tegra) } if (ufs_tegra->x2config) { mphy_writel(ufs_tegra->mphy_l1_base, MPHY_EQ_TIMEOUT, - MPHY_RX_APB_VENDOR3B_0_T234); + MPHY_RX_APB_VENDOR3B_0_T234); mphy_update(ufs_tegra->mphy_l1_base, MPHY_GO_BIT, MPHY_RX_APB_VENDOR2_0_T234); err = mphy_go_bit_status(ufs_tegra->mphy_l1_base, MPHY_RX_APB_VENDOR2_0_T234); - if (err) { + if (err) dev_err(dev, "%s: Go bit clear failed for mphy1\n", __func__); - } } end: return err; } -static void ufs_tegra_jtag(struct ufs_tegra_host *ufs_tegra, u32 addr, u32 val) -{ - struct ufs_hba *hba = ufs_tegra->hba; - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8192, 0x4), ((addr >> 8) & (0xff))); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8193, 0x4), (addr & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8194, 0x4), 0x0); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4), 0x2); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4), 0x0); - udelay(3); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8192, 0x4), ((val >> 8) & (0xff))); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8193, 0x4), (val & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8194, 0x4), 0x1); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4), 0x2); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4), 0x0); - udelay(3); -} - -static void writeC10RegBank(struct ufs_tegra_host *ufs_tegra, u32 addr, u32 val) -{ - struct ufs_hba *hba = ufs_tegra->hba; - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0016, 0x0), (addr & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0017, 0x0), ((addr >> 8) & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0018, 0x0), (val & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0019, 0x0), ((val >> 8) & 0xff)); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x001c, 0x0), 0x1); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0), 0x1); - udelay(1); - -} - -static void waitCfgRdyN_TX(struct ufs_tegra_host *ufs_tegra) -{ - struct ufs_hba *hba = ufs_tegra->hba; - int cfg_rdy_n = 1; - u32 read_data = 0; - - while (cfg_rdy_n == 1) { - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xd08e, 0x0), &read_data); - cfg_rdy_n = ((read_data >> 16) & 0x1); - read_data = 0; - } - -} - -static void waitCfgRdyN_RX(struct ufs_tegra_host *ufs_tegra) -{ - struct ufs_hba *hba = ufs_tegra->hba; - int cfg_rdy_n = 1; - u32 read_data = 0; - - while (cfg_rdy_n == 1) { - ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0xd08e, 0x0), &read_data); - cfg_rdy_n = ((read_data >> 10) & 0x1); - read_data = 0; - } -} - -static void ufs_tegra_mphy_startup_sequence(struct ufs_tegra_host *ufs_tegra) -{ - struct ufs_hba *hba = ufs_tegra->hba; - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819f, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819f, 0x4U), 0x0U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819e, 0x4U), 0x21U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819e, 0x4), 0x0U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819a, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819a, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819a, 0x4U), 0x4U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819c, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819c, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x819c, 0x4U), 0x4U); - - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818c, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818c, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818c, 0x4U), 0x4U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818d, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818d, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818d, 0x4U), 0x4U); - - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818e, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818e, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818e, 0x4U), 0x4U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818f, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818f, 0x4U), 0x14U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x818f, 0x4U), 0x4U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0c1, 0x0U), 0x1U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8190, 0x4U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8190, 0x4U), 0x10U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8190, 0x4U), 0x0U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4U), 0x4U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4U), 0x0U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8191, 0x4U), 0x31U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8195, 0x4U), 0x0U); - - ufs_tegra_jtag(ufs_tegra, 0x400a, 0x26); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8185, 0x4U), 0x3U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8185, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8185, 0x4U), 0x2U); - - - ufs_tegra_jtag(ufs_tegra, 0x2002, 0x1); - ufs_tegra_jtag(ufs_tegra, 0x200a, 0x01bf); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8184, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8189, 0x4U), 0x1aU); - - ufs_tegra_jtag(ufs_tegra, 0x3007U, 0x70U); - ufs_tegra_jtag(ufs_tegra, 0x3107U, 0x70U); - ufs_tegra_jtag(ufs_tegra, 0x3004U, 0x2040U); - ufs_tegra_jtag(ufs_tegra, 0x3104U, 0x2040U); - - - ufs_tegra_jtag(ufs_tegra, 0x2003U, 0x260U); - ufs_tegra_jtag(ufs_tegra, 0x2004U, 0x4bU); - ufs_tegra_jtag(ufs_tegra, 0x3006U, 0x540U); - ufs_tegra_jtag(ufs_tegra, 0x3005U, 0x1e87U); - ufs_tegra_jtag(ufs_tegra, 0x3106U, 0x540U); - ufs_tegra_jtag(ufs_tegra, 0x3105U, 0x1e87U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8182, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8114, 0x0U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x811f, 0x0U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8132, 0x0U), 0x80U); - - - waitCfgRdyN_TX(ufs_tegra); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x4U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8013, 0x4U), 0x2U); - - waitCfgRdyN_RX(ufs_tegra); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x10U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x4U), 0x2U); - waitCfgRdyN_RX(ufs_tegra); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x10U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x5U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8013, 0x5U), 0x2U); - waitCfgRdyN_RX(ufs_tegra); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x20U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x008f, 0x5U), 0x2U); - waitCfgRdyN_RX(ufs_tegra); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x20U); - - writeC10RegBank(ufs_tegra, 0x401c, 0x0004); - writeC10RegBank(ufs_tegra, 0x411c, 0x0004); - writeC10RegBank(ufs_tegra, 0x10ae, 0x0001); - writeC10RegBank(ufs_tegra, 0x10ad, 0x0080); - writeC10RegBank(ufs_tegra, 0x10af, 0x001a); - writeC10RegBank(ufs_tegra, 0x10b6, 0x0001); - writeC10RegBank(ufs_tegra, 0x10AE, 0x0000); - writeC10RegBank(ufs_tegra, 0x11AE, 0x0001); - writeC10RegBank(ufs_tegra, 0x11AD, 0x0080); - writeC10RegBank(ufs_tegra, 0x11AF, 0x001A); - writeC10RegBank(ufs_tegra, 0x11B6, 0x0001); - writeC10RegBank(ufs_tegra, 0x11AE, 0x0000); - writeC10RegBank(ufs_tegra, 0x1002, 0xAD00); - writeC10RegBank(ufs_tegra, 0x1102, 0xAD00); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0c1, 0x0U), 0x0U); - waitCfgRdyN_TX(ufs_tegra); - mdelay(200); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x002b, 0x0U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x002b, 0x1U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x2U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x1U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x0U), 0x0); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800a, 0x0U), 0x64U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8009, 0x1U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x800a, 0x1U), 0x64U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8011, 0x4U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8012, 0x4U), 0x64U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8011, 0x5U), 0x0U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8012, 0x5), 0x64U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x2U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x1U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x20U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd0fa, 0x0U), 0x10U); - - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x1564, 0x0U), 0x80U); - ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xd086, 0x0U), 0x80U); -} #if defined(CONFIG_TEGRA_PROD_LEGACY) static void ufs_tegra_prod_settings(struct ufs_tegra_host *ufs_tegra) @@ -2207,17 +1754,17 @@ static void ufs_tegra_prod_settings(struct ufs_tegra_host *ufs_tegra) err = tegra_prod_set_by_name(&ufs_tegra->mphy_l0_base, "prod", ufs_tegra->prod_list); if (err < 0) { dev_info_once(ufs_tegra->hba->dev, - "Prod config not found for mphy0: %d\n", err); + "Prod config not found for mphy0: %d\n", err); return; } if (ufs_tegra->x2config) { - err = tegra_prod_set_by_name(&ufs_tegra->mphy_l1_base, "prod", ufs_tegra->prod_list); + err = tegra_prod_set_by_name(&ufs_tegra->mphy_l1_base, "prod", + ufs_tegra->prod_list); if (err < 0) dev_info_once(ufs_tegra->hba->dev, - "Prod config not found for mphy1: %d\n", err); + "Prod config not found for mphy1: %d\n", err); } - return; } #endif @@ -2275,7 +1822,7 @@ static int ufs_tegra_init(struct ufs_hba *hba) ufs_virt_addr_range = UFS_AUX_ADDR_VIRT_RANGE_264; virt_ctrl_en = UFS_AUX_ADDR_VIRT_CTRL_EN | UFS_AUX_ADDR_VIRT_PA_VA_CTRL; - } else if (ufs_tegra->soc->chip_id == TEGRA234) { + } else { ufs_aux_base_addr = NV_ADDRESS_MAP_T23X_UFSHC_AUX_BASE; ufs_aux_addr_range = UFS_AUX_ADDR_RANGE_23X; mphy_l0_addr_base = NV_ADDRESS_MAP_MPHY_L0_BASE; @@ -2287,48 +1834,41 @@ static int ufs_tegra_init(struct ufs_hba *hba) #if defined(NV_UFSHCD_QUIRKS_ENUM_HAS_UFSHCD_QUIRK_BROKEN_POWER_SEQUENCE) ufs_tegra->hba->quirks |= UFSHCD_QUIRK_BROKEN_PWR_SEQUENCE; #endif - } else { - ufs_aux_base_addr = NV_ADDRESS_MAP_UFSHC_AUX_BASE; - ufs_aux_addr_range = UFS_AUX_ADDR_RANGE; - mphy_l0_addr_base = NV_ADDRESS_MAP_MPHY_L0_BASE; - mphy_l1_addr_base = NV_ADDRESS_MAP_MPHY_L1_BASE; - mphy_addr_range = MPHY_ADDR_RANGE; } - ufs_tegra->ufs_aux_base = devm_ioremap(dev, - ufs_aux_base_addr, ufs_aux_addr_range); + ufs_tegra->ufs_aux_base = devm_ioremap(dev, ufs_aux_base_addr, + ufs_aux_addr_range); if (!ufs_tegra->ufs_aux_base) { err = -ENOMEM; dev_err(dev, "ufs_aux_base ioremap failed\n"); goto out; } - ufs_tegra->mphy_l0_base = devm_ioremap(dev, - mphy_l0_addr_base, mphy_addr_range); + ufs_tegra->mphy_l0_base = devm_ioremap(dev, mphy_l0_addr_base, + mphy_addr_range); if (!ufs_tegra->mphy_l0_base) { err = -ENOMEM; dev_err(dev, "mphy_l0_base ioremap failed\n"); goto out; } - ufs_tegra->mphy_l1_base = devm_ioremap(dev, - mphy_l1_addr_base, mphy_addr_range); + ufs_tegra->mphy_l1_base = devm_ioremap(dev, mphy_l1_addr_base, + mphy_addr_range); if (!ufs_tegra->mphy_l1_base) { err = -ENOMEM; dev_err(dev, "mphy_l1_base ioremap failed\n"); goto out; } - if (ufs_tegra->soc->chip_id >= TEGRA234) { - hba->caps |= UFSHCD_CAP_WB_EN; - ufs_tegra->ufs_virtualization_base = devm_ioremap(dev, - ufs_virt_base_addr, - ufs_virt_addr_range); - if (!ufs_tegra->ufs_virtualization_base) { - err = -ENOMEM; - dev_err(dev, "UFS Virtualization failed\n"); - goto out; - } + hba->caps |= UFSHCD_CAP_WB_EN; + ufs_tegra->ufs_virtualization_base = + devm_ioremap(dev, + ufs_virt_base_addr, + ufs_virt_addr_range); + if (!ufs_tegra->ufs_virtualization_base) { + err = -ENOMEM; + dev_err(dev, "UFS Virtualization failed\n"); + goto out; } #if defined(CONFIG_TEGRA_PROD_LEGACY) @@ -2369,7 +1909,7 @@ static int ufs_tegra_init(struct ufs_hba *hba) goto out_host_free; if (ufs_tegra->soc->chip_id != TEGRA264) { err = ufs_tegra_host_clk_enable(dev, "mphy_force_ls_mode", - ufs_tegra->mphy_force_ls_mode); + ufs_tegra->mphy_force_ls_mode); if (err) goto out_host_free; usleep_range(1000, 2000); @@ -2418,26 +1958,23 @@ aux_init: goto out_disable_mphylane_clks; end: - if (ufs_tegra->soc->chip_id >= TEGRA234) { - fwspec = dev_iommu_fwspec_get(dev); - if (fwspec == NULL) { - dev_err(dev, "Failed to get MC streamid. Continuing\n"); - } else { - ufs_tegra->streamid = fwspec->ids[0] & 0xffff; - writel(virt_ctrl_en, - ufs_tegra->ufs_virtualization_base + - UFS_AUX_ADDR_VIRT_CTRL_0); - writel(ufs_tegra->streamid, - ufs_tegra->ufs_virtualization_base + - UFS_AUX_ADDR_VIRT_REG_0); - } + fwspec = dev_iommu_fwspec_get(dev); + if (!fwspec) { + dev_err(dev, "Failed to get MC streamid. Continuing\n"); + } else { + ufs_tegra->streamid = fwspec->ids[0] & 0xffff; + writel(virt_ctrl_en, + ufs_tegra->ufs_virtualization_base + + UFS_AUX_ADDR_VIRT_CTRL_0); + writel(ufs_tegra->streamid, + ufs_tegra->ufs_virtualization_base + + UFS_AUX_ADDR_VIRT_REG_0); } #if defined(CONFIG_TEGRA_PROD_LEGACY) /* Configure prod values */ ufs_tegra_prod_settings(ufs_tegra); #endif - if (ufs_tegra->soc->chip_id > TEGRA234) { err = ufs_tegra_pwr_change_clk_boost(ufs_tegra); if (err) @@ -2474,12 +2011,7 @@ static void ufs_tegra_exit(struct ufs_hba *hba) #if defined(NV_UFS_HBA_VARIANT_OPS_HAS_SET_DMA_MASK) /* Linux v6.13 */ static int ufs_tegra_set_dma_mask(struct ufs_hba *hba) { - struct ufs_tegra_host *ufs_tegra = hba->priv; - - if (ufs_tegra->soc->chip_id >= TEGRA234) - return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); - - return 0; + return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); } #endif @@ -2513,16 +2045,19 @@ static int ufs_tegra_probe(struct platform_device *pdev) /* Do not enable ufs on non-rdl part*/ err = tegra_fuse_readl(TEGRA_FUSE_OPT_LOT_CODE_0_0, &value); if (err) { - dev_err(dev, "%s rdl fuse read failed err: %d val: %#x\n", __func__, err, value); + dev_err(dev, "%s rdl fuse read failed err: %d val: %#x\n", + __func__, err, value); goto end; } - if ((value == NON_RDL_STRUCTURE) || - (value == NON_RDL_LEAD)) { - dev_info(dev, "%s This is non-rdl part. No support for UFS %#x\n", __func__, value); + if (value == NON_RDL_STRUCTURE || + value == NON_RDL_LEAD) { + dev_info(dev, "%s This is non-rdl part. No support for UFS %#x\n", + __func__, value); err = -ENODEV; goto end; } else { - dev_dbg(dev, "%s This is rdl part. UFS is supported %#x\n", __func__, value); + dev_dbg(dev, "%s This is rdl part. UFS is supported %#x\n", __func__, + value); } } @@ -2543,13 +2078,8 @@ static int ufs_tegra_remove(struct platform_device *pdev) pm_runtime_get_sync(&(pdev)->dev); ufshcd_remove(hba); return 0; - } -static struct ufs_tegra_soc_data tegra194_soc_data = { - .chip_id = TEGRA194, -}; - static struct ufs_tegra_soc_data tegra234_soc_data = { .chip_id = TEGRA234, }; @@ -2562,9 +2092,6 @@ static struct ufs_tegra_soc_data tegra264_soc_data = { static const struct of_device_id ufs_tegra_of_match[] = { { - .compatible = "tegra194,ufs_variant", - .data = &tegra194_soc_data, - }, { .compatible = "tegra234,ufs_variant", .data = &tegra234_soc_data, #if defined(NV_TEGRA264_CHIP_ID_PRESENT) /* Linux v6.5 */ diff --git a/drivers/scsi/ufs/ufs-tegra.h b/drivers/scsi/ufs/ufs-tegra.h index 637734d4..ba00cab4 100644 --- a/drivers/scsi/ufs/ufs-tegra.h +++ b/drivers/scsi/ufs/ufs-tegra.h @@ -1,6 +1,5 @@ -/* SPDX-License-Identifier: GPL-2.0-only - */ -// Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. #ifndef _UFS_TEGRA_H #define _UFS_TEGRA_H @@ -15,7 +14,6 @@ #define NV_ADDRESS_MAP_MPHY_L1_BASE 0x02480000 #define NV_ADDRESS_MAP_T23X_UFSHC_VIRT_BASE 0x02520000 #define MPHY_ADDR_RANGE_T234 0x2268 -#define MPHY_ADDR_RANGE 0x200 #define UFS_AUX_ADDR_VIRT_RANGE_23X 0x14f #define NV_ADDRESS_MAP_MPHY_L0_BASE_T264 0xa80b910000 @@ -26,17 +24,11 @@ /* UFS AUX address range in T264 */ #define UFS_AUX_ADDR_RANGE_264 0x100 - /* UFS VIRTUALIZATION address for T264 */ #define NV_ADDRESS_MAP_T264_UFSHC_VIRT_BASE 0xa80b8f0000 /* UFS VIRTUALIZATION range in T264 */ #define UFS_AUX_ADDR_VIRT_RANGE_264 0x200 -/* UFS AUX Base address for T194 */ -#define NV_ADDRESS_MAP_UFSHC_AUX_BASE 0x02460000 -/* UFS AUX address range in T194 */ -#define UFS_AUX_ADDR_RANGE 0x1C - /* UFS AUX Base address for T234 */ #define NV_ADDRESS_MAP_T23X_UFSHC_AUX_BASE 0x02510000 /* UFS AUX address range in T234 */ @@ -80,10 +72,10 @@ #define MPHY_TX_APB_TX_CLK_CTRL0_0_T234 0x1160 #define MPHY_TX_APB_TX_CLK_CTRL2_0_T234 0x1168 -#define MPHY_TX_CLK_EN_SYMB (1 << 1) -#define MPHY_TX_CLK_EN_SLOW (1 << 3) -#define MPHY_TX_CLK_EN_FIXED (1 << 4) -#define MPHY_TX_CLK_EN_3X (1 << 5) +#define MPHY_TX_CLK_EN_SYMB BIT(1) +#define MPHY_TX_CLK_EN_SLOW BIT(3) +#define MPHY_TX_CLK_EN_FIXED BIT(4) +#define MPHY_TX_CLK_EN_3X BIT(5) #define MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 0x34 #define TX_ADVANCED_GRANULARITY (0x8 << 16) @@ -114,18 +106,17 @@ #define RX_ADVANCED_MIN_ACTIVATETIME(x) (((x) & 0xf) << 16) #define RX_ADVANCED_MIN_AT 0xa - #define MPHY_RX_APB_VENDOR2_0 0x184 #define MPHY_RX_APB_VENDOR2_0_T234 0x2184 #define MPHY_RX_APB_VENDOR3_0 0x188 #define MPHY_RX_APB_VENDOR3_0_T234 0x2188 -#define MPHY_RX_APB_VENDOR2_0_RX_CAL_EN (1 << 15) -#define MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE (1 << 19) -#define MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL (1 << 26) +#define MPHY_RX_APB_VENDOR2_0_RX_CAL_EN BIT(15) +#define MPHY_RX_APB_VENDOR2_0_RX_CAL_DONE BIT(19) +#define MPHY_ENABLE_RX_MPHY2UPHY_IF_OVR_CTRL BIT(26) #define MPHY_TX_APB_TX_VENDOR2_0_T264 0x1108 -#define MPHY_TX_APB_VENDOR2_0_TX_CAL_EN (1 << 15) -#define MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE (1 << 19) +#define MPHY_TX_APB_VENDOR2_0_TX_CAL_EN BIT(15) +#define MPHY_TX_APB_VENDOR2_0_TX_CAL_DONE BIT(19) #define MPHY_RX_CAPABILITY_88_8B_VAL_FPGA 0x4f00fa1a #define MPHY_RX_CAPABILITY_8C_8F_VAL_FPGA 0x50e080e @@ -186,32 +177,29 @@ enum ufs_state { #define UFS_VNDR_HCLKDIV_1US_TICK_T264 0xD0 #define UFS_VNDR_HCLKDIV_1US_TICK_FPGA 0x1A - /*UFS host controller vendor specific registers */ enum { REG_UFS_VNDR_HCLKDIV = 0xFC, }; - /* * UFS AUX Registers */ #define UFSHC_AUX_UFSHC_STATUS_0 0x10 -#define UFSHC_HIBERNATE_STATUS (1 << 0) +#define UFSHC_HIBERNATE_STATUS BIT(0) #define UFSHC_AUX_UFSHC_DEV_CTRL_0 0x14 -#define UFSHC_DEV_CLK_EN (1 << 0) -#define UFSHC_DEV_RESET (1 << 1) +#define UFSHC_DEV_CLK_EN BIT(0) +#define UFSHC_DEV_RESET BIT(1) #define UFSHC_AUX_UFSHC_SW_EN_CLK_SLCG_0 0x08 -#define UFSHC_CLK_OVR_ON (1 << 0) -#define UFSHC_HCLK_OVR_ON (1 << 1) -#define UFSHC_LP_CLK_T_CLK_OVR_ON (1 << 2) -#define UFSHC_CLK_T_CLK_OVR_ON (1 << 3) -#define UFSHC_CG_SYS_CLK_OVR_ON (1 << 4) -#define UFSHC_TX_SYMBOL_CLK_OVR_ON (1 << 5) -#define UFSHC_RX_SYMBOLCLKSELECTED_CLK_OVR_ON (1 << 6) -#define UFSHC_PCLK_OVR_ON (1 << 7) - +#define UFSHC_CLK_OVR_ON BIT(0) +#define UFSHC_HCLK_OVR_ON BIT(1) +#define UFSHC_LP_CLK_T_CLK_OVR_ON BIT(2) +#define UFSHC_CLK_T_CLK_OVR_ON BIT(3) +#define UFSHC_CG_SYS_CLK_OVR_ON BIT(4) +#define UFSHC_TX_SYMBOL_CLK_OVR_ON BIT(5) +#define UFSHC_RX_SYMBOLCLKSELECTED_CLK_OVR_ON BIT(6) +#define UFSHC_PCLK_OVR_ON BIT(7) #define PA_SCRAMBLING 0x1585 #define PA_PEERSCRAMBLING 0x155B @@ -229,114 +217,6 @@ enum { #define DME_TC0REPLAYTIMEOUTVAL 0xD042 #define DME_AFC0REQTIMEOUTVAL 0xD043 -/* - * MPHY Context save armphy_rx_apb registers - */ - -static u16 __attribute__ ((unused)) mphy_rx_apb[] = { -0x080, /* MPHY_RX_APB_CAPABILITY_80_83_0 */ -0x084, /* MPHY_RX_APB_CAPABILITY_84_87_0 */ -0x088, /* MPHY_RX_APB_CAPABILITY_88_8B_0 */ -0x08c, /* MPHY_RX_APB_CAPABILITY_8C_8F_0 */ -0x090, /* MPHY_RX_APB_CAPABILITY_90_93_0 */ -0x094, /* MPHY_RX_APB_CAPABILITY_94_97_0 */ -0x098, /* MPHY_RX_APB_CAPABILITY_98_9B_0 */ -0x0a0, /* MPHY_RX_APB_ATTRIBUTE_A0_A3_0 */ -0x0a4, /* MPHY_RX_APB_ATTRIBUTE_A4_A7_0 */ -0x0a8, /* MPHY_RX_APB_ATTRIBUTE_A8_AB_0 */ -0x0d0, /* MPHY_RX_APB_MC_STATUS_D0_D3_0 */ -0x0d4, /* MPHY_RX_APB_MC_STATUS_D4_D7_0 */ -0x0d8, /* MPHY_RX_APB_MC_STATUS_D8_DB_0 */ -0x0dc, /* MPHY_RX_APB_MC_STATUS_DC_DF_0 */ -0x0e0, /* MPHY_RX_APB_MC_STATUS_E0_E3_0 */ -0x0e4, /* MPHY_RX_APB_MC_STATUS_E4_E7_0 */ -0x180, /* MPHY_RX_APB_VENDOR1_0 */ -0x184, /* MPHY_RX_APB_VENDOR2_0 */ -0x188, /* MPHY_RX_APB_VENDOR3_0 */ -0x18c, /* MPHY_RX_APB_VENDOR4_0 */ -0x190, /* MPHY_RX_APB_VENDOR5_0 */ -0x194, /* MPHY_RX_APB_VENDOR6_0 */ -0x198, /* MPHY_RX_APB_VENDOR7_0 */ -0x19c, /* MPHY_RX_APB_VENDOR8_0 */ -0x1a0, /* MPHY_RX_APB_VENDOR9_0 */ -0x1a4, /* MPHY_RX_APB_VENDOR10_0 */ -0x1a8, /* MPHY_RX_APB_VENDOR11_0 */ -0x1ac, /* MPHY_RX_APB_VENDOR12_0 */ -0x1b0, /* MPHY_RX_APB_VENDOR13_0 */ -0x1b4, /* MPHY_RX_APB_VENDOR14_0 */ -0x1b8, /* MPHY_RX_APB_VENDOR15_0 */ -0x1bc, /* MPHY_RX_APB_VENDOR16_0 */ -0x1c0, /* MPHY_RX_APB_VENDOR17_0 */ -0x1c4, /* MPHY_RX_APB_VENDOR18_0 */ -0x1c8, /* MPHY_RX_APB_VENDOR19_0 */ -0x1cc, /* MPHY_RX_APB_VENDOR20_0 */ -0x1d0, /* MPHY_RX_APB_VENDOR21_0 */ -0x1d4, /* MPHY_RX_APB_VENDOR22_0 */ -0x1d8, /* MPHY_RX_APB_VENDOR23_0 */ -0x1dc, /* MPHY_RX_APB_VENDOR24_0 */ -0x1e0, /* MPHY_RX_APB_VENDOR25_0 */ -0x1e4, /* MPHY_RX_APB_VENDOR26_0 */ -0x1e8, /* MPHY_RX_APB_VENDOR27_0 */ -0x1ec, /* MPHY_RX_APB_VENDOR28_0 */ -0x1f0, /* MPHY_RX_APB_VENDOR29_0 */ -0x1f4, /* MPHY_RX_APB_VENDOR30_0 */ -0x1f8, /* MPHY_RX_APB_VENDOR31_0 */ -0x1fc /* MPHY_RX_APB_VENDOR32_0 */ -}; - -/* - * MPHY Context save armphy_tx_apb registers - */ - -static u16 __attribute__ ((unused)) mphy_tx_apb[] = { -0x000, /* MPHY_TX_APB_TX_CAPABILITY_00_03_0 */ -0x004, /* MPHY_TX_APB_TX_CAPABILITY_04_07_0 */ -0x008, /* MPHY_TX_APB_TX_CAPABILITY_08_0B_0 */ -0x00c, /* MPHY_TX_APB_TX_CAPABILITY_0C_0F_0 */ -0x010, /* MPHY_TX_APB_TX_CAPABILITY_10_13_0 */ -0x020, /* MPHY_TX_APB_TX_ATTRIBUTE_20_23_0 */ -0x024, /* MPHY_TX_APB_TX_ATTRIBUTE_24_27_0 */ -0x028, /* MPHY_TX_APB_TX_ATTRIBUTE_28_2B_0 */ -0x02c, /* MPHY_TX_APB_TX_ATTRIBUTE_2C_2F_0 */ -0x030, /* MPHY_TX_APB_TX_ATTRIBUTE_30_33_0 */ -0x034, /* MPHY_TX_APB_TX_ATTRIBUTE_34_37_0 */ -0x038, /* MPHY_TX_APB_TX_ATTRIBUTE_38_3B_0 */ -0x060, /* MPHY_TX_APB_MC_ATTRIBUTE_60_63_0 */ -0x064, /* MPHY_TX_APB_MC_ATTRIBUTE_64_67_0 */ -0x100, /* MPHY_TX_APB_TX_VENDOR0_0 */ -0x104, /* MPHY_TX_APB_TX_VENDOR1_0 */ -0x108, /* MPHY_TX_APB_TX_VENDOR2_0 */ -0x10c, /* MPHY_TX_APB_TX_VENDOR3_0 */ -0x110, /* MPHY_TX_APB_TX_VENDOR4_0 */ -0x114, /* MPHY_TX_APB_TX_VENDOR5_0 */ -0x118, /* MPHY_TX_APB_TX_VENDOR6_0 */ -0x11c, /* MPHY_TX_APB_TX_VENDOR7_0 */ -0x120, /* MPHY_TX_APB_PAD_TIMING0_0 */ -0x124, /* MPHY_TX_APB_PAD_TIMING1_0 */ -0x128, /* MPHY_TX_APB_PAD_TIMING2_0 */ -0x12c, /* MPHY_TX_APB_PAD_TIMING3_0 */ -0x130, /* MPHY_TX_APB_PAD_TIMING4_0 */ -0x134, /* MPHY_TX_APB_PAD_TIMING5_0 */ -0x138, /* MPHY_TX_APB_PAD_TIMING6_0 */ -0x13c, /* MPHY_TX_APB_PAD_TIMING7_0 */ -0x140, /* MPHY_TX_APB_PAD_TIMING8_0 */ -0x144, /* MPHY_TX_APB_PAD_TIMING9_0 */ -0x148, /* MPHY_TX_APB_PAD_TIMING10_0 */ -0x14c, /* MPHY_TX_APB_TX_PAD_OVR_VAL0_0 */ -0x150, /* MPHY_TX_APB_TX_PAD_OVR_CTRL0_0 */ -0x154, /* MPHY_TX_APB_TX_OVR_CTRL0_0 */ -0x158, /* MPHY_TX_APB_TX_OVR_VAL0_0 */ -0x15c, /* MPHY_TX_APB_PAD_TIMER0_0 */ -0x160, /* MPHY_TX_APB_TX_CLK_CTRL0_0 */ -0x164, /* MPHY_TX_APB_TX_CLK_CTRL1_0 */ -0x168, /* MPHY_TX_APB_TX_CLK_CTRL2_0 */ -0x16c, /* MPHY_TX_APB_TX_CLK_CTRL3_0 */ -0x170, /* MPHY_TX_APB_TX_CG_OVR0_0 */ -0x174, /* MPHY_TX_APB_TX_CG_COUNTER0_0 */ -0x178, /* MPHY_TX_APB_TX_PAD_OVR_VAL1_0 */ -0x17c /* MPHY_TX_APB_TX_PAD_OVR_CTRL1_0 */ -}; - struct ufs_tegra_soc_data { u8 chip_id; }; @@ -345,7 +225,6 @@ struct ufs_tegra_host { struct ufs_hba *hba; bool is_lane_clks_enabled; bool x2config; - bool enable_mphy_rx_calib; bool enable_hs_mode; bool enable_38mhz_clk; bool enable_ufs_provisioning; @@ -400,11 +279,6 @@ struct ufs_tegra_host { struct pinctrl_state *dpd_enable; struct pinctrl_state *dpd_disable; u32 vs_burst; - /* Hibernate entry support is broken - WAR is suggested to fix hibernate entry functionality - */ - #define NVQUIRK_BROKEN_HIBERN8_ENTRY UTP_TRANSFER_REQ_COMPL - /* UFS tegra deviations from standard UFSHCI spec. */ unsigned int nvquirks; bool wake_enable_failed; @@ -430,8 +304,6 @@ struct ufs_tegra_host { }; extern struct ufs_hba_variant_ops ufs_hba_tegra_vops; -extern int ufshcd_rescan(struct ufs_hba *hb); -void ufs_rescan(struct work_struct *work); static inline u32 mphy_readl(void __iomem *mphy_base, u32 offset) { @@ -451,8 +323,7 @@ static inline void mphy_writel(void __iomem *mphy_base, u32 val, u32 offset) writel(val, mphy_base + offset); } -static inline void mphy_update(void __iomem *mphy_base, u32 val, - u32 offset) +static inline void mphy_update(void __iomem *mphy_base, u32 val, u32 offset) { u32 update_val; @@ -461,8 +332,7 @@ static inline void mphy_update(void __iomem *mphy_base, u32 val, mphy_writel(mphy_base, update_val, offset); } -static inline void mphy_clear_bits(void __iomem *mphy_base, u32 val, - u32 offset) +static inline void mphy_clear_bits(void __iomem *mphy_base, u32 val, u32 offset) { u32 update_val; @@ -480,13 +350,13 @@ static inline u32 ufs_aux_readl(void __iomem *ufs_aux_base, u32 offset) } static inline void ufs_aux_writel(void __iomem *ufs_aux_base, u32 val, - u32 offset) + u32 offset) { writel(val, ufs_aux_base + offset); } static inline void ufs_aux_update(void __iomem *ufs_aux_base, u32 val, - u32 offset) + u32 offset) { u32 update_val; @@ -496,7 +366,7 @@ static inline void ufs_aux_update(void __iomem *ufs_aux_base, u32 val, } static inline void ufs_aux_clear_bits(void __iomem *ufs_aux_base, u32 val, - u32 offset) + u32 offset) { u32 update_val; @@ -506,7 +376,7 @@ static inline void ufs_aux_clear_bits(void __iomem *ufs_aux_base, u32 val, } static inline void ufs_save_regs(void __iomem *reg_base, u32 *save_addr, - u16 reg_array[], u32 no_of_regs) + u16 reg_array[], u32 no_of_regs) { u32 regs; u32 *dest = save_addr; @@ -516,7 +386,7 @@ static inline void ufs_save_regs(void __iomem *reg_base, u32 *save_addr, } static inline void ufs_restore_regs(void __iomem *reg_base, u32 *save_addr, - u16 reg_array[], u32 no_of_regs) + u16 reg_array[], u32 no_of_regs) { u32 regs; u32 *src = save_addr;