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drivers: Enable -Wmissing-prototypes

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The compiler option -Wmissing-prototypes is being enabled globally in
the upstream Linux kernel and this causes build failures for various
drivers. The build failures occur because either the driver is missing
an include file which has the prototype or because the function is not
declared statically when it should be (ie. there are no external users).

Fix the various build failures and enable -Wmissing-prototypes to
prevent any new instances from occurring. Note that the only driver that
is not fixed at the moment is rtl8822ce due to large number of failures
and so build this with '-Wno-missing-prototypes' for now, which is not
different to how it was being compiled prior to this change.

Bug 4404965

Change-Id: Ie5572d23659e0346fa035d645d9043b0a6da5fdc
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3027488
(cherry picked from commit d5391a25ab)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3034644
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Jon Hunter
2023-12-04 10:00:13 +00:00
committed by mobile promotions
parent 7f3751f642
commit 069d6bb3eb
20 changed files with 55 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
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@@ -5,6 +5,7 @@ LINUXINCLUDE += -I$(srctree.nvconftest)
LINUXINCLUDE += -I$(srctree.nvidia-oot)/include LINUXINCLUDE += -I$(srctree.nvidia-oot)/include
subdir-ccflags-y += -Werror subdir-ccflags-y += -Werror
subdir-ccflags-y += -Wmissing-prototypes
LINUX_VERSION := $(shell expr $(VERSION) \* 256 + $(PATCHLEVEL)) LINUX_VERSION := $(shell expr $(VERSION) \* 256 + $(PATCHLEVEL))
LINUX_VERSION_6_2 := $(shell expr 6 \* 256 + 2) LINUX_VERSION_6_2 := $(shell expr 6 \* 256 + 2)

2
drivers/crypto/tegra/tegra-se-hash.c
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@@ -492,7 +492,7 @@ digbuf_fail:
return -ENOMEM; return -ENOMEM;
} }
int tegra_hmac_fallback_setkey(struct tegra_sha_ctx *ctx, const u8 *key, static int tegra_hmac_fallback_setkey(struct tegra_sha_ctx *ctx, const u8 *key,
unsigned int keylen) unsigned int keylen)
{ {
if (!ctx->fallback_tfm) { if (!ctx->fallback_tfm) {

1
drivers/gpu/drm/tegra/drm.c
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@@ -26,6 +26,7 @@
#include <drm/drm_ioctl.h> #include <drm/drm_ioctl.h>
#include <drm/drm_prime.h> #include <drm/drm_prime.h>
#include <drm/drm_vblank.h> #include <drm/drm_vblank.h>
#include <drm/tegra_drm-next.h>
#if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
#include <asm/dma-iommu.h> #include <asm/dma-iommu.h>

2
drivers/gpu/host1x/cdma.c
View File

@@ -496,7 +496,7 @@ resume:
host1x_hw_cdma_resume(host1x, cdma, restart_addr); host1x_hw_cdma_resume(host1x, cdma, restart_addr);
} }
void cdma_update_work(struct work_struct *work) static void cdma_update_work(struct work_struct *work)
{ {
struct host1x_cdma *cdma = container_of(work, struct host1x_cdma, update_work); struct host1x_cdma *cdma = container_of(work, struct host1x_cdma, update_work);

5
drivers/media/i2c/nv_hawk_owl.c
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@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All Rights Reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* /*
* nv_hawk_owl.c.c - ar0234 sensor driver * nv_hawk_owl.c.c - ar0234 sensor driver
*/ */
@@ -15,6 +15,7 @@
#include <linux/of_gpio.h> #include <linux/of_gpio.h>
#include <media/max9295.h> #include <media/max9295.h>
#include <media/max9296.h> #include <media/max9296.h>
#include <media/nv_hawk_owl.h>
#include <media/tegracam_core.h> #include <media/tegracam_core.h>
#include "hawk_owl_mode_tbls.h" #include "hawk_owl_mode_tbls.h"
#include <linux/ktime.h> #include <linux/ktime.h>

2
drivers/net/ethernet/realtek/r8168_n.c
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@@ -2113,7 +2113,7 @@ static u32 rtl8168_mdio_real_read_phy_ocp(struct rtl8168_private *tp,
return mdio_real_direct_read_phy_ocp(tp, ocp_addr); return mdio_real_direct_read_phy_ocp(tp, ocp_addr);
} }
u32 mdio_real_read(struct rtl8168_private *tp, static u32 mdio_real_read(struct rtl8168_private *tp,
u32 RegAddr) u32 RegAddr)
{ {
int i, value = 0; int i, value = 0;

2
drivers/net/ethernet/realtek/rtl_eeprom.c
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@@ -93,7 +93,7 @@ void rtl8168_eeprom_cleanup(struct rtl8168_private *tp)
rtl8168_lower_clock(tp, &x); rtl8168_lower_clock(tp, &x);
} }
int rtl8168_eeprom_cmd_done(struct rtl8168_private *tp) static int rtl8168_eeprom_cmd_done(struct rtl8168_private *tp)
{ {
u8 x; u8 x;
int i; int i;

1
drivers/net/wireless/realtek/rtl8822ce/Makefile
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@@ -18,6 +18,7 @@ EXTRA_CFLAGS += -Wno-implicit-fallthrough
EXTRA_CFLAGS += -Wno-unused-function EXTRA_CFLAGS += -Wno-unused-function
#EXTRA_CFLAGS += -Wno-unused #EXTRA_CFLAGS += -Wno-unused
#EXTRA_CFLAGS += -Wno-uninitialized #EXTRA_CFLAGS += -Wno-uninitialized
EXTRA_CFLAGS += -Wno-missing-prototypes
GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc ) GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
ifeq ($(GCC_VER_49),1) ifeq ($(GCC_VER_49),1)

5
drivers/platform/tegra/dce/dce-debug-perf.c
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@@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
*/
#include <linux/errno.h> #include <linux/errno.h>
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#include <dce.h> #include <dce.h>
#include <dce-debug-perf.h>
#include <dce-log.h> #include <dce-log.h>
#include <dce-util-common.h> #include <dce-util-common.h>
#include <interface/dce-interface.h> #include <interface/dce-interface.h>

7
drivers/platform/tegra/nvadsp/os.c
View File

@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/** // SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <nvidia/conftest.h> #include <nvidia/conftest.h>
#include <linux/init.h> #include <linux/init.h>
@@ -324,7 +323,7 @@ bool is_adsp_dram_addr(u64 addr)
return false; return false;
} }
int is_cluster_mem_addr(u64 addr) static int is_cluster_mem_addr(u64 addr)
{ {
int clust_id; int clust_id;
struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv.pdev); struct nvadsp_drv_data *drv_data = platform_get_drvdata(priv.pdev);

4
drivers/platform/tegra/tegra_bootloader_debug.c
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <linux/init.h> #include <linux/init.h>
#include <linux/module.h> #include <linux/module.h>
@@ -19,6 +19,8 @@
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include "tegra_bootloader_debug.h"
static phys_addr_t tegra_bl_debug_data_start; static phys_addr_t tegra_bl_debug_data_start;
static phys_addr_t tegra_bl_debug_data_size; static phys_addr_t tegra_bl_debug_data_size;
static phys_addr_t tegra_bl_prof_start; static phys_addr_t tegra_bl_prof_start;

11
drivers/platform/tegra/tegra_bootloader_debug.h Normal file
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@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SPDX-FileCopyrightText: Copyright (C) 2023 NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __TEGRA_BOOTLOADER_DEBUG_H
#define __TEGRA_BOOTLOADER_DEBUG_H
size_t tegra_bl_add_profiler_entry(const char *buf, size_t len);
#endif

6
drivers/tty/serial/wch_35x/wch_main.c
View File

@@ -734,7 +734,7 @@ void ch365_32s_test(void)
} }
#endif #endif
int wch_register_irq(void) static int wch_register_irq(void)
{ {
struct wch_board *sb = NULL; struct wch_board *sb = NULL;
int status = 0; int status = 0;
@@ -784,7 +784,7 @@ int wch_register_irq(void)
return status; return status;
} }
void wch_iounmap(void) static void wch_iounmap(void)
{ {
struct wch_board *sb = NULL; struct wch_board *sb = NULL;
int i; int i;
@@ -802,7 +802,7 @@ void wch_iounmap(void)
} }
} }
void wch_release_irq(void) static void wch_release_irq(void)
{ {
struct wch_board *sb = NULL; struct wch_board *sb = NULL;
int i; int i;

4
drivers/video/tegra/host/nvcsi/nvcsi.c
View File

@@ -1,8 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* /*
* NVCSI driver * NVCSI driver
*
* Copyright (c) 2014-2022, NVIDIA Corporation. All rights reserved.
*/ */
#include <linux/device.h> #include <linux/device.h>
#include <linux/export.h> #include <linux/export.h>
@@ -28,6 +27,7 @@
//#include "camera/nvcsi/csi5_fops.h" //#include "camera/nvcsi/csi5_fops.h"
#include "deskew.h" #include "deskew.h"
#include "nvcsi.h"
#define PG_CLK_RATE 102000000 #define PG_CLK_RATE 102000000
/* width of interface between VI and CSI */ /* width of interface between VI and CSI */

5
drivers/video/tegra/host/pva/nvpva_syncpt.c
View File

@@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* // SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/nvhost.h> #include <linux/nvhost.h>
@@ -11,6 +9,7 @@
#include <linux/iommu.h> #include <linux/iommu.h>
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include "pva.h" #include "pva.h"
#include "nvpva_syncpt.h"
int nvpva_map_region(struct device *dev, int nvpva_map_region(struct device *dev,
phys_addr_t start, phys_addr_t start,

5
drivers/video/tegra/host/pva/pva_ccq_t23x.c
View File

@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/* /*
* Copyright (c) 2017-2023, NVIDIA CORPORATION. All rights reserved.
*
* PVA Command Queue Interface handling * PVA Command Queue Interface handling
*/ */
@@ -104,7 +103,7 @@ void pva_ccq_isr_handler(struct pva *pva, unsigned int queue_id)
wake_up(&pva->cmd_waitqueue[cmd_status_index]); wake_up(&pva->cmd_waitqueue[cmd_status_index]);
} }
int pva_ccq_wait_event(struct pva *pva, unsigned int queue_id, int wait_time) static int pva_ccq_wait_event(struct pva *pva, unsigned int queue_id, int wait_time)
{ {
int timeout = 1; int timeout = 1;
int err; int err;

6
drivers/video/tegra/host/pva/pva_dma.c
View File

@@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* // SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
@@ -37,7 +35,7 @@ static const u8 max_desc_id[4] = {
[PVA_HW_GEN3] = NVPVA_TASK_MAX_DMA_DESCRIPTOR_ID_T26X [PVA_HW_GEN3] = NVPVA_TASK_MAX_DMA_DESCRIPTOR_ID_T26X
}; };
int static int
pitch_linear_eq_offset(struct nvpva_dma_descriptor const *dma_desc, pitch_linear_eq_offset(struct nvpva_dma_descriptor const *dma_desc,
s64 *frame_buf_offset, s64 *frame_buf_offset,
const int64_t surf_bl_offset, const int64_t surf_bl_offset,

5
drivers/video/tegra/host/pva/pva_sec_ec.c
View File

@@ -1,11 +1,10 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*/
#include <linux/nvhost.h> #include <linux/nvhost.h>
#include "pva_regs.h" #include "pva_regs.h"
#include "pva.h" #include "pva.h"
#include "pva_sec_ec.h"
static u32 pva_get_sec_ec_addrs(u32 index) static u32 pva_get_sec_ec_addrs(u32 index)
{ {

6
drivers/video/tegra/host/pva/pva_vpu_app_auth.c
View File

@@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* // SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved.
*/
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/types.h> #include <linux/types.h>
@@ -21,7 +19,7 @@ struct pva_buff_s {
uint32_t size; uint32_t size;
}; };
s32 read_buff(struct pva_buff_s *src_buf, void *dst, u32 size) static s32 read_buff(struct pva_buff_s *src_buf, void *dst, u32 size)
{ {
u32 pos = src_buf->pos + size; u32 pos = src_buf->pos + size;

11
include/media/nv_hawk_owl.h Normal file
View File

@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* SPDX-FileCopyrightText: Copyright (C) 2023 NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __NV_HAWK_OWL_H
#define __NV_HAWK_OWL_H
int Hawk_Owl_Fsync_program(int fsync_type);
#endif