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dt-bindings: nvethernet: nvethernet DT binding doc
Captures the DT binding documentation for the nvethernet driver Bug 3837018 Change-Id: Ifd77ae28499e41d7134777f088063871b36f0e88 Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/2911843 Reviewed-by: Narayan Reddy <narayanr@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/platform/tegra/tegra-nvethernet.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Device tree binding for NVIDIA Tegra Ethernet Controller
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maintainers:
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- Revanth Kumar Uppala <ruppala@nvidia.com>
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description: |
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The tegra nvethernet driver provides an interface for communication over ethernet.
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properties:
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compatible:
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enum:
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- For EQOS: should be "nvidia,nveqos"
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- FOR MGBE: should be "nvidia,nvmgbe"
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reg:
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description: |
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Physical base address and size of register space.
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reg-names:
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description: |
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Specifies the names of the registers.
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interrupts:
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description: |
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An array of tuples specifying IRQ number for
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each tx/rx queue in case of multi-queue, and
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for the only tx/rx queue,in case of single queue
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EQOS has a common interrupt for triggering any
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non DMA channel interrupts like link up/down.
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Order of interrupts need to be listed as common,
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Tx followed by Rx interrupts.
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interrupt-names:
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description: |
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Specifies the names of the interrupts.
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clocks:
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description: |
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Holds Phandle and clock specifiers in same
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order for each entry in clock-names property.
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clock-names:
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description: |
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Specifies the names of the needed clocks.
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resets:
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description: |
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Holds Phandle and rest specifiers in the same
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order for each entry in reset-names property.
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reset-names:
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description: |
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Specifies the name of the reset line.
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iommus:
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description: |
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A list of phandle and IOMMU specifier pairs that
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describe the IOMMU master interfaces of the
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device. IOMMU specifier points stream ID used
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for IP which can be used for address translation.
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interconnects :
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description: |
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Pairs of phandles and interconnect provider specifier to denote
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the edge source and destination ports of the interconnect path.
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An optional path tag value could specified as additional argument
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to both endpoints and in such cases, this information will be
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passed to the interconnect framework to do aggregation based on
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the attached tag.
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interconnect-names :
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description: |
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List of interconnect path name strings sorted in the same
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order as the interconnects property. Consumers drivers will use
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interconnect-names to match interconnect paths with interconnect
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specifier pairs.
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nvidia,num-dma-chans:
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description: |
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Number of DMA channels that need to be used.
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For EQOS, Minimum value is 1 and Maximum value is 8.
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For MGBE, Minimum value is 1 and Maximum value is 10.
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nvidia,dma-chans:
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description: |
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The channel number of DMA channels to be used.
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Number of channels provided here should be equal
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to the value in nvidia,num-dma-chans property.
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For EQOS, Valid numbers are 0,1,2,3,4,5,6,7
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For MGBE, Valid numbers are 0,1,2,3,4,5,6,7,8,9
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nvidia,num-mtl-queues:
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description: |
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Number of MTL Queues that need to be used.
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For EQOS, Minimum value is 1 and Maximum value is 8.
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For MGBE, Minimum value is 1 and Maximum value is 10.
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nvidia,mtl-queues:
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description: |
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Queues that need to be filled based on the
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nvidia,mtl-queues.
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For EQOS, Valid numbers are 0,1,2,3,4,5,6,7
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For MGBE, Valid numbers are 0,1,2,3,4,5,6,7,8,9
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nvidia,tc-mapping:
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description: |
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Traffic class mapping for TxQ. This will map
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Transmit queue to a traffic class. Default
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mapping is 1:1 between TxQ and TC class. Valid
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property for IP with more number queue than TC.
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nvidia,residual-queue:
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description: |
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Residual Queue to receive untagged Preempted
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fragments. RxQ0 can't be residual queue.
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nvidia,rx-queue-prio:
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description: |
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When a bit is uniquely set in this property
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i.e. same bit map shall not be set in multiple bytes of this
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property, it means the tagged packet with that
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priority will be routed to the Rx queue
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specified in nvidia,mtl-queues property at the
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same index position.
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For EQOS, Each byte in this property is a bit map of
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individual vlan priorities 0 to 7.
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For MGBE, Each byte in this property is a bit map of
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individual vlan priorities 0 to 9.
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nvidia,tx-queue-prio:
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description: |
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When this is set, it means the packet with that priority
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will be routed to the Tx queue specified in
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nvidia,mtl-queues property at the same index
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position.
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For EQOS, Each byte in this property is a bit map of
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individual vlan priorities 0 to 7.
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For MGBE, Each byte in this property is a bit map of
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individual vlan priorities 0 to 9.
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nvidia,rxq_enable_ctrl:
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description: |
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Mode of the MTL Receive Queue to enable either
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AV mode or legacy mode.
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example - rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
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0x0 = Not enabled, 0x1 = Enabled for AV
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0x2 = Enabled for Legacy, 0x3 = Reserved
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nvidia,dcs-enable:
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description: |
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Enable this to dynamically select the most suitable channel
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for data transmission when high interference is detected on
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the current channel.
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Dynamic Channel Selection enable(1) or
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disable(0). This property is mutually
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exclusive with rx-queue-prio i.e. if this is
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enabled, then rx-queue-prio should not be
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provided and vice versa.
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nvidia,pad_calibration:
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description: |
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Specifies if pad calibration should be allowed
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or not. Set to 1 to allow or 0 to disallow
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pad calibration mode. Default is 1 (allowed).
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nvidia,pad_auto_cal_pu_offset:
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description: |
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Specifies eqos ETHER_QOS_AUTO_CAL_CONFIG_0
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reg, pad calibration 2's complement offset
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for pull-up value. Allowed range 0x0-0x1F.
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Default is 0 (allowed).
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nvidia,pad_auto_cal_pd_offset:
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description: |
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Specifies eqos ETHER_QOS_AUTO_CAL_CONFIG_0
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reg, pad calibration 2's complement offset
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for pull-down value. Allowed range 0x0-0x1F.
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Default is 0 (allowed).
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nvidia,rx_riwt:
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description: |
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Specifies the RX wathcdog interrupt timeout in
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usec.The RIWT field is programmed as
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(<val> * 256) / 62.5. if rx_riwt is 0 then RIWT
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is disabled and IOC will be enabled. Minimum
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value is 3 and Maximum value is 1020.
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nvidia,rx_frames:
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description: |
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Specifies the RX frame count for interrupt
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coalescing. If rx_frames is 0 then RX frame
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count based interrupt coalescing is disabled and
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Rx interrupt will be triggered based on rx_riwt
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value.
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For EQOS, Minimum value for rx_frames is 1 and
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Maximum value is 256.
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For MGBE, Minimum value for rx_frames is 1 and
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Maximum value is 4096.
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nvidia,tx_usecs:
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description: |
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Specifies the TX software timer interrupt
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timeout in usec. if tx_usecs is 0 then TX
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software timer is disabled and Tx interrupt
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will be triggered for each packet. Minimum
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value is 32 and Maximum value is 1020.
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nvidia,tx_frames:
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description: |
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Specifies the TX frame count for interrupt
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coalescing. If tx_frames is 0 then TX frame
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count based interrupt coalescing is disabled and
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Tx interrupt will be triggered based on tx_usecs
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value.
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For EQOS, Minimum value for tx_frames is 1 and
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Maximum value is 10.
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For MGBE, Minimum value for tx_frames is 1 and
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Maximum value is 170.
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nvidia,promisc_mode:
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description: |
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Specifies if promiscuous mode should be allowed
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or not. Set to 1 to allow or 0 to disallow
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promiscuous mode. Default is 1 (allowed).
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nvidia,slot_num_check:
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description: |
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List of flags (0x0 to disable, 0x1 to enable)
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to configure slot function per DMA channel.
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Once this flag is enabled the corresponding TX
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queue will be configured in AVB Strict priority
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mode, not in CBS mode. So it will starve
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TX queue 0 hence it is recommended to enable
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CBS to set bandwidth limits as per use case.
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The TX queue 0 can't be programmed for AVB mode,
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so the corresponding DMA channel can't be
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configured for slot function.
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nvidia,slot_intvl_vals:
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description: |
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List of slot intervals (with a range from 1usec
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to 4096usec) for fetching the data from
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system memory per DMA channel give in
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the dma-chans property. If this is not
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specified 125usec default will be used.
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nvidia,ptp_ref_clock_speed:
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description: |
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This is reference for PTP clock frequency and
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the value set for tegra is 312.5MHz.
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The frequency of this clock is programmable and
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can be configured based on the requirements.
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The maximum frequency it can take is 312.5MHz
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and minimum frequency is 25MHz
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FOR EQOS, Value set is 208.3MHz
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FOR MGBE, Value set is 312.5MHz.
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nvidia,instance_id:
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description: |
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Ethernet interface instance id. Fixed id value
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is used. For mgbe0 is 0, mgbe1 is 1,
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mgbe2 is 2, mgbe3 is 3 and eqos is 4.
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nvidia,ptp-rx-queue:
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description: |
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This field specifies the Rx queue on which the
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untagged PTP packets sent over the Ethernet
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payload (not over IPv4 or IPv6) are routed.
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dma-coherent:
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description: |
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Present if dma operations are coherent.
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nvidia,ptp_m2m_role:
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description: |
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Ethernet HW role in PTP MAC-TO-MAC time sync.
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This DT property holds the value to identify
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role of HW. Ethernet HW can act as primary
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interface(1), secondary interface(2) or
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inactive interface(0). By default all HW are
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inactive interface if DT property not defined.
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nvidia,skip_mac_reset:
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description: |
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Flag to skip MAC reset from driver.
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1 = skip doing mac reset, 0 = okay to reset.
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nvidia,mac-addr-idx:
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description: |
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Chosen node inside DT will updated with list of
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MAC addresses in increasing order up to the
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maximum MAC addresses based on platform
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configuration.
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This DT property holds the value (index)
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to fetch from the MAC address list inside
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chosen node. This is read only property for
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a given platform.
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example - If there is Ethernet controller DT node
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with index 8, the controller MAC address
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is at /chosen/nvidia,ether-mac8.
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nvidia,dma_rx_ring_sz:
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description: |
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Specifies the RX ring size.
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For EQOS values are 64, 128, 256, 512, and 1024.
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For MGBE values are 64, 128, 256, 512, 1024, 2048, and 4096.
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nvidia,dma_tx_ring_sz:
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description: |
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Specifies the TX ring size.
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For EQOS values are 64, 128, 256, 512, and 1024.
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For MGBE values are 64, 128, 256, 512, 1024, 2048, and 4096.
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status:
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description: |
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To disable and enable the VF DT node.Values should
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be okay/disable.
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nvidia,if-name:
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description: |
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Specifies interface name of the VF.This will be derived from name
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and uint as <<if name prefix>><<DMA channel no>>
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If name prefix -
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For EQOS use eoqs_
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For MGBE0 use mgbe0_
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For MGBE1 use mgbe1_
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For MGBE2 use mgbe2_
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For MGBE3 use mgbe3_
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DMA channel no -
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Use DMA channel number given in the DT node.
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nvidia,uphy-gbe-mode:
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description: |
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Specifies Gigabit Ethernet mode for UPHY.
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1 = 10G, 0 = 5G.
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nvidia,phy-iface-mode:
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description: |
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Specifies PHY interface mode.
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0 = XFI 10G, 1 = XFI 5G, 2 = USXGMII 10G, 3 = USXGMII 5G.
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nvidia,mdio_addr:
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description: |
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Specifies the MDIO address of the PHY.
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nvidia,phy:
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description: |
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Specifies the name of the PHY used by Ethernet controller.
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For MGBE0, value is "88Q4364".
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nvidia,max-platform-mtu:
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description: |
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Maximum MTU size supported for a platform.
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currently it is set to 9000 for embedded
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platforms. if DT entry is not
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present then it will be set to 1500 for
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automotive platforms. In case of automotive
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platforms MAC is connected to a switch and not
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to PHY directly. The switch limits the max MTU
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to 1500B, hence this property is used to
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prevent configuring MTU size greater than 1500B
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for EQOS contoller as well. In case of
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embedded platforms MAC is connected directly to
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PHY and hence MTU size of up to 9018 is supported
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(9022 in case of tagged frame).
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nvidia,macsec-enable:
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description: |
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Initialization of the MACsec happens only if this property
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is enabled.
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0x1= enable, 0x0=disable.
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nvidia,vm-irq-config:
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description: |
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Specifies IRQ data and IRQ numbers for different VMs.
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nvidia,ptp-tsc-trig:
|
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description: |
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Specifies the trigger time interval in which PTP-TSC timestamp
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capture is triggered.
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0 = disable, 1 to UINT32_MAX = trigger time in ms.
|
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pinctrl-names:
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description: |
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If we define this property, then we can control
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EQOS pin-mux states dynamically so that we can
|
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save power based on the Ethernet link.
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pinctrl-0:
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description: |
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||||
Valid only when "pictrl-names" is defined, this
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property has the configuration that need to be
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set to EQOS signals when Ethernet link is down.
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pinctrl-1:
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description: |
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||||
Valid only when "pinctrl-names" is defined, this
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||||
property has the configuration that need to be
|
||||
set when Ethernet link is up.
|
||||
|
||||
phy-mode:
|
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description: |
|
||||
Operation mode of the PHY interface and it
|
||||
should be "rgmii-id".
|
||||
|
||||
phy-handle:
|
||||
description: |
|
||||
Phandle, specifies a reference to a node
|
||||
representing a PHY device.
|
||||
|
||||
#MDIO node
|
||||
|
||||
mdio:
|
||||
description: |
|
||||
Child of Ethernet controller which holds the PHY
|
||||
devices connected via MDIO bus.
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,eqos-mdio
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||||
|
||||
#PHY nodes
|
||||
|
||||
reg:
|
||||
description: |
|
||||
PHY ID number.
|
||||
|
||||
#Fixed Link
|
||||
|
||||
fixed-link:
|
||||
description: |
|
||||
Some Ethernet MACs have a "fixed link", and are not connected
|
||||
to a normal MDIO-managed PHY device. For those situations,
|
||||
a Device Tree binding allows to describe a "fixed link".
|
||||
|
||||
speed:
|
||||
description: |
|
||||
Specifies the link speed.
|
||||
Accepted values are 10, 100, 1000, 5000 and 10000.
|
||||
|
||||
full-duplex:
|
||||
description: |
|
||||
To indicate that full duplex is used.
|
||||
When absent, half duplex is assumed.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- iommus
|
||||
- interconnects
|
||||
- interconnect-names
|
||||
- nvidia,num-dma-chans
|
||||
- nvidia,dma-chans
|
||||
- nvidia,num-mtl-queues
|
||||
- nvidia,mtl-queues
|
||||
- nvidia,tc-mapping
|
||||
- nvidia,residual-queue
|
||||
- nvidia,rx-queue-prio
|
||||
- nvidia,tx-queue-prio
|
||||
- nvidia,rxq_enable_ctrl
|
||||
- nvidia,dcs-enable
|
||||
- nvidia,pad_calibration
|
||||
- nvidia,pad_auto_cal_pu_offset
|
||||
- nvidia,pad_auto_cal_pd_offset
|
||||
- nvidia,rx_riwt
|
||||
- nvidia,rx_frames
|
||||
- nvidia,tx_usecs
|
||||
- nvidia,tx_frames
|
||||
- nvidia,promisc_mode
|
||||
- nvidia,slot_num_check
|
||||
- nvidia,slot_intvl_vals
|
||||
- nvidia,ptp_ref_clock_speed
|
||||
- nvidia,instance_id
|
||||
- nvidia,ptp-rx-queue
|
||||
- dma-coherent
|
||||
- nvidia,ptp_m2m_role
|
||||
- nvidia,skip_mac_reset
|
||||
- nvidia,mac-addr-idx
|
||||
- nvidia,dma_rx_ring_sz
|
||||
- nvidia,dma_tx_ring_sz
|
||||
- status
|
||||
- nvidia,if-name
|
||||
- nvidia,uphy-gbe-mode
|
||||
- nvidia,phy-iface-mode
|
||||
- nvidia,mdio_addr
|
||||
- nvidia,phy
|
||||
- nvidia,max-platform-mtu
|
||||
- nvidia,macsec-enable
|
||||
- nvidia,vm-irq-config
|
||||
- nvidia,ptp-tsc-trig
|
||||
- pinctrl-names
|
||||
- pinctrl-0
|
||||
- pinctrl-1
|
||||
- phy-mode
|
||||
- phy-handle
|
||||
- mdio
|
||||
- compatible
|
||||
- reg
|
||||
- fixed-link
|
||||
- speed
|
||||
- full-duplex
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
#EQOS
|
||||
examples:
|
||||
- |
|
||||
ethernet@2310000 {
|
||||
compatible = "nvidia,nveqos";
|
||||
reg = <0x0 0x02310000 0x0 0x10000>, /* EQOS Base Register */
|
||||
<0x0 0x023D0000 0x0 0x10000>, /* MACSEC Base Register */
|
||||
<0x0 0x02300000 0x0 0x10000>; /* HV Base Register */
|
||||
reg-names = "mac", "macsec-base", "hypervisor";
|
||||
interrupts = <0 194 0x4>, /* common */
|
||||
<0 186 0x4>, /* vm0 */
|
||||
<0 187 0x4>, /* vm1 */
|
||||
<0 188 0x4>, /* vm2 */
|
||||
<0 189 0x4>, /* vm3 */
|
||||
<0 190 0x4>, /* MACsec non-secure intr */
|
||||
<0 191 0x4>; /* MACsec secure intr */
|
||||
interrupt-names = "common", "vm0", "vm1", "vm2", "vm3",
|
||||
"macsec-ns-irq", "macsec-s-irq";
|
||||
resets = <&bpmp TEGRA234_RESET_EQOS>,
|
||||
<&bpmp TEGRA234_RESET_EQOS_MACSEC>; /* MACsec non-secure reset */
|
||||
reset-names = "mac", "macsec_ns_rst";
|
||||
clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_AXI>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_RX>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_TX>,
|
||||
<&bpmp TEGRA234_CLK_AXI_CBB>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_RX_M>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
|
||||
<&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
|
||||
clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx",
|
||||
"eqos_ptp_ref", "eqos_tx", "axi_cbb",
|
||||
"eqos_rx_m", "eqos_rx_input",
|
||||
"eqos_macsec_tx", "eqos_tx_divider",
|
||||
"eqos_macsec_rx";
|
||||
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
#endif
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
|
||||
nvidia,num-dma-chans = <8>;
|
||||
nvidia,num-mtl-queues = <8>;
|
||||
nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
|
||||
nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
|
||||
nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
|
||||
/* Residual Queue can be any valid queue except RxQ0 */
|
||||
nvidia,residual-queue = <1>;
|
||||
nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
|
||||
nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
|
||||
nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
|
||||
nvidia,vm-irq-config = <&eqos_vm_irq_config>;
|
||||
nvidia,dcs-enable = <0x1>;
|
||||
nvidia,macsec-enable = <0x1>;
|
||||
nvidia,pad_calibration = <0x1>;
|
||||
/* pad calibration 2's complement offset for pull-down value */
|
||||
nvidia,pad_auto_cal_pd_offset = <0x0>;
|
||||
/* pad calibration 2's complement offset for pull-up value */
|
||||
nvidia,pad_auto_cal_pu_offset = <0x0>;
|
||||
nvidia,rx_riwt = <512>;
|
||||
nvidia,rx_frames = <64>;
|
||||
nvidia,tx_usecs = <256>;
|
||||
nvidia,tx_frames = <5>;
|
||||
nvidia,promisc_mode = <1>;
|
||||
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
|
||||
nvidia,ptp_ref_clock_speed = <208333334>;
|
||||
nvidia,instance_id = <4>; /* EQOS instance */
|
||||
nvidia,ptp-rx-queue = <3>;
|
||||
pinctrl-names = "mii_rx_disable", "mii_rx_enable";
|
||||
pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
|
||||
pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
|
||||
nvidia,dma_rx_ring_sz = <1024>;
|
||||
nvidia,dma_tx_ring_sz = <1024>;
|
||||
dma-coherent;
|
||||
nvidia,ptp_m2m_role = <2>;
|
||||
status = "okay";
|
||||
nvidia,if-name = "eqos_0";
|
||||
nvidia,mac-addr-idx = <0>;
|
||||
nvidia,skip_mac_reset = <1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&phy>;
|
||||
nvidia,ptp-tsc-trig = <500>;
|
||||
/delete-node/ fixed-link;
|
||||
|
||||
mdio {
|
||||
compatible = "nvidia,eqos-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#MGBE
|
||||
examples:
|
||||
- |
|
||||
ethernet@6810000 {
|
||||
compatible = "nvidia,nvmgbe";
|
||||
reg = <0x0 0x06810000 0x0 0x10000>, /* MGBE base */
|
||||
<0x0 0x068A0000 0x0 0x10000>, /* XPCS base */
|
||||
<0x0 0x068D0000 0x0 0x10000>, /* MACsec RM base */
|
||||
<0x0 0x06800000 0x0 0x10000>; /* HV base */
|
||||
reg-names = "mac", "xpcs", "macsec-base", "hypervisor";
|
||||
interrupts = <0 384 0x4>, /* common */
|
||||
<0 385 0x4>, /* vm0 */
|
||||
<0 386 0x4>, /* vm1 */
|
||||
<0 387 0x4>, /* vm2 */
|
||||
<0 388 0x4>, /* vm3 */
|
||||
<0 389 0x4>, /* vm4 */
|
||||
<0 390 0x4>, /* MACsec non-secure intr */
|
||||
<0 391 0x4>; /* MACsec secure intr */
|
||||
interrupt-names = "common", "vm0", "vm1", "vm2", "vm3", "vm4",
|
||||
"macsec-ns-irq", "macsec-s-irq";
|
||||
resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
|
||||
<&bpmp TEGRA234_RESET_MGBE0_PCS>,
|
||||
<&bpmp TEGRA234_RESET_MGBE0_MACSEC>; /* MACsec non-secure reset */
|
||||
reset-names = "mac", "pcs", "macsec_ns_rst";
|
||||
clocks = <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_TX>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_TX_PCS>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_MAC>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_APP>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_MACSEC>,
|
||||
<&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>;
|
||||
clock-names = "rx-input-m", "rx-pcs-m", "rx-pcs-input",
|
||||
"rx-pcs", "tx", "tx-pcs", "mac-divider",
|
||||
"mac", "eee-pcs", "mgbe", "ptp-ref",
|
||||
"mgbe_macsec", "rx-input";
|
||||
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_MGBEAWR>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
#endif
|
||||
iommus = <&smmu_niso0 TEGRA_SID_NISO0_MGBE>;
|
||||
nvidia,num-dma-chans = <10>;
|
||||
nvidia,dma-chans = <0 1 2 3 4 5 6 7 8 9>;
|
||||
nvidia,num-mtl-queues = <10>;
|
||||
nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
|
||||
nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
|
||||
/* Residual Queue can be any valid queue except RxQ0 */
|
||||
nvidia,residual-queue = <1>;
|
||||
nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
|
||||
nvidia,vm-irq-config = <&mgbe_vm_irq_config>;
|
||||
nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
|
||||
nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
|
||||
nvidia,dcs-enable = <0x1>;
|
||||
nvidia,macsec-enable = <0x1>;
|
||||
nvidia,rx_riwt = <512>;
|
||||
nvidia,rx_frames = <64>;
|
||||
nvidia,tx_usecs = <256>;
|
||||
nvidia,tx_frames = <16>;
|
||||
nvidia,promisc_mode = <1>;
|
||||
nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
|
||||
nvidia,ptp_ref_clock_speed = <312500000>;
|
||||
nvidia,instance_id = <0>; /* MGBE0 instance */
|
||||
nvidia,ptp-rx-queue = <3>;
|
||||
nvidia,dma_rx_ring_sz = <4096>;
|
||||
nvidia,dma_tx_ring_sz = <4096>;
|
||||
dma-coherent;
|
||||
status = "okay";
|
||||
nvidia,if-name = "mgbe0_0";
|
||||
nvidia,mac-addr-idx = <2>;
|
||||
nvidia,skip_mac_reset = <1>;
|
||||
nvidia,mdio_addr = <0>;
|
||||
nvidia,phy = "88Q4364";
|
||||
/* 1:10G, 0:5G */
|
||||
nvidia,uphy-gbe-mode = <1>;
|
||||
/* 0:XFI 10G, 1:XFI 5G, 2:USXGMII 10G, 3:USXGMII 5G */
|
||||
nvidia,phy-iface-mode = <0>;
|
||||
nvidia,max-platform-mtu = <9215>;
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
...
|
||||
Reference in New Issue
Block a user