nv-tegra-mirror/linux-nv-oot
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nv-oot.git synced 2025-12-22 17:25:35 +03:00
Code Issues Packages Projects Releases Wiki Activity

host1x_emu: Enable event-service for Host1x-EMU

Browse Source 
Add change to host1x-fence kernel module to support
its functionality over host1x-emu driver.

Jira HOSTX-5818

Change-Id: I09c7f2ee2059e0eeee11429b059c5152ffd855d5
Signed-off-by: amitabhd <amitabhd@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3285249
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
amitabhd
2025-01-17 06:33:04 +00:00
committed by Jon Hunter
parent 3e0be33037
commit 090b44a9f1
4 changed files with 20 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/host1x-emu/fence.c
View File

@@ -178,6 +178,20 @@ HOST1X_EMU_EXPORT_DECL(int, host1x_fence_extract(struct dma_fence *dfence, u32 *
} }
HOST1X_EMU_EXPORT_SYMBOL(host1x_fence_extract); HOST1X_EMU_EXPORT_SYMBOL(host1x_fence_extract);
HOST1X_EMU_EXPORT_DECL(int, host1x_fence_get_node(struct dma_fence *dfence))
{
struct host1x_syncpt_fence *sf;
int node;
if (dfence->ops != &host1x_syncpt_fence_ops)
return -EINVAL;
sf = to_host1x_fence(dfence);
node = dev_to_node(sf->sp->host->dev);
return node == NUMA_NO_NODE ? 0 : node;
}
HOST1X_EMU_EXPORT_SYMBOL(host1x_fence_get_node);
HOST1X_EMU_EXPORT_DECL(void, host1x_fence_cancel(struct dma_fence *dfence)) HOST1X_EMU_EXPORT_DECL(void, host1x_fence_cancel(struct dma_fence *dfence))
{ {
struct host1x_syncpt_fence *sf = to_host1x_fence(dfence); struct host1x_syncpt_fence *sf = to_host1x_fence(dfence);

2
drivers/gpu/host1x-emu/include/linux/host1x-emu.h
View File

@@ -78,6 +78,8 @@ HOST1X_EMU_EXPORT_DECL(struct dma_fence*, host1x_fence_create(struct host1x_sync
HOST1X_EMU_EXPORT_DECL(int, host1x_fence_extract(struct dma_fence *fence, u32 *id, u32 *threshold)); HOST1X_EMU_EXPORT_DECL(int, host1x_fence_extract(struct dma_fence *fence, u32 *id, u32 *threshold));
HOST1X_EMU_EXPORT_DECL(int, host1x_fence_get_node(struct dma_fence *fence));
HOST1X_EMU_EXPORT_DECL(void, host1x_fence_cancel(struct dma_fence *fence)); HOST1X_EMU_EXPORT_DECL(void, host1x_fence_cancel(struct dma_fence *fence));
#endif #endif

4
drivers/gpu/host1x-fence/dev.c
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include <nvidia/conftest.h> #include <nvidia/conftest.h>
@@ -36,6 +36,7 @@ static int dev_file_open(struct inode *inode, struct file *file)
struct host1x **host1xp; struct host1x **host1xp;
static const struct of_device_id host1x_match[] = { static const struct of_device_id host1x_match[] = {
{ .compatible = "nvidia,tegraEmu-host1x", },
{ .compatible = "nvidia,tegra186-host1x", }, { .compatible = "nvidia,tegra186-host1x", },
{ .compatible = "nvidia,tegra194-host1x", }, { .compatible = "nvidia,tegra194-host1x", },
{ .compatible = "nvidia,tegra234-host1x", }, { .compatible = "nvidia,tegra234-host1x", },
@@ -544,6 +545,7 @@ unregister_chrdev_region:
} }
static const struct of_device_id host1x_fence_of_match[] = { static const struct of_device_id host1x_fence_of_match[] = {
{ .compatible = "nvidia,tegraEmu-host1x" },
{ .compatible = "nvidia,tegra234-host1x" }, { .compatible = "nvidia,tegra234-host1x" },
{ .compatible = "nvidia,tegra264-host1x" }, { .compatible = "nvidia,tegra264-host1x" },
{ }, { },