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nvethernet:set clocks based on serdes speed

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1) set eqos rx clock based on serdes speed
2) set mgbe app parent based on serdes speed

Bug 4713751

Change-Id: If776c84807f7aa0373e1106c218b60da51921e79
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3166928
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This commit is contained in:
Narayan Reddy
2024-07-02 16:33:50 +00:00
committed by mobile promotions
parent 083d7038d1
commit 0bca2438be
2 changed files with 219 additions and 23 deletions
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15
drivers/net/ethernet/nvidia/nvethernet/ether_linux.h
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@@ -150,6 +150,11 @@
#define ETHER_EQOS_TX_CLK_10M 2500000UL
#define ETHER_EQOS_UPHY_LX_TX_2_5G_CLK 195312500UL
#define ETHER_EQOS_UPHY_LX_TX_1G_CLK 78125000UL
#define ETHER_EQOS_RX_PCS_CLK_2_5G 312500000UL
#define ETHER_EQOS_RX_CLK_1000M 125000000UL
#define ETHER_EQOS_UPHY_LX_RX_2_5G_CLK 195312500UL
#define ETHER_MGBE_APP_25G_CLK 650000000UL
#define ETHER_MGBE_APP_10G_5G_CLK 480000000UL
/**
* @brief 1 Second in Neno Second
@@ -498,6 +503,16 @@ struct ether_priv_data {
struct clk *app_clk;
/** MAC Rx input clk */
struct clk *rx_input_clk;
/** PLL refgp_out1 clock */
struct clk *pllrefgp_out1;
/** utmi_pll1_clkout480 clock*/
struct clk *utmi_pll1_clkout480;
/** pll_bpmpcam clock */
struct clk *pll_bpmpcam;
/** Tx serdes clock */
struct clk *tx_ser_clk;
/** Rx serdes clock */
struct clk *rx_ser_clk;
/** Pointer to PHY device tree node */
struct device_node *phy_node;
/** Pointer to MDIO device tree node */