diff --git a/drivers/spi/spi-tegra124-slave.c b/drivers/spi/spi-tegra124-slave.c index 10ffee53..c48d03ee 100644 --- a/drivers/spi/spi-tegra124-slave.c +++ b/drivers/spi/spi-tegra124-slave.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: Copyright (C) 2023 NVIDIA CORPORATION. All rights reserved. +// SPDX-FileCopyrightText: Copyright (C) 2023-2024 NVIDIA CORPORATION. All rights reserved. + +#include #include #include @@ -1357,7 +1359,11 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, command1 |= SPI_TX_EN; tspi->cur_direction |= DATA_DIR_TX; } +#if defined(NV_SPI_GET_CHIPSELECT_PRESENT) + command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0)); +#else command1 |= SPI_CS_SEL(spi->chip_select); +#endif tegra_spi_writel(tspi, command1, SPI_COMMAND1); tspi->command1_reg = command1; @@ -1398,7 +1404,11 @@ static struct tegra_spi_controller_data return NULL; } +#if defined(NV_SPI_GET_CHIPSELECT_PRESENT) + cdata = &tspi->cdata[spi_get_chipselect(spi, 0)]; +#else cdata = &tspi->cdata[spi->chip_select]; +#endif memset(cdata, 0, sizeof(*cdata)); ret = of_property_read_bool(data_np, "nvidia,variable-length-transfer"); @@ -1448,10 +1458,17 @@ static int tegra_spi_setup(struct spi_device *spi) spin_lock_irqsave(&tspi->lock, flags); val = tspi->def_command1_reg; +#if defined(NV_SPI_GET_CHIPSELECT_PRESENT) + if (spi->mode & SPI_CS_HIGH) + val &= ~cs_pol_bit[spi_get_chipselect(spi, 0)]; + else + val |= cs_pol_bit[spi_get_chipselect(spi, 0)]; +#else if (spi->mode & SPI_CS_HIGH) val &= ~cs_pol_bit[spi->chip_select]; else val |= cs_pol_bit[spi->chip_select]; +#endif if (tspi->lsbyte_first) val |= SPI_LSBYTE_FE; diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index c7a7a631..170c6a37 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only -// -// Copyright (C) 2023 NVIDIA CORPORATION. +// SPDX-FileCopyrightText: Copyright (C) 2023-2024 NVIDIA CORPORATION. All rights reserved. + +#include #include #include @@ -925,7 +926,11 @@ static u32 tegra_qspi_setup_transfer_one(struct spi_device *spi, struct spi_tran tegra_qspi_mask_clear_irq(tqspi); command1 = tqspi->def_command1_reg; +#if defined(NV_SPI_GET_CHIPSELECT_PRESENT) + command1 |= QSPI_CS_SEL(spi_get_chipselect(spi, 0)); +#else command1 |= QSPI_CS_SEL(spi->chip_select); +#endif command1 |= QSPI_BIT_LENGTH(bits_per_word - 1); command1 &= ~QSPI_CONTROL_MODE_MASK; @@ -1109,11 +1114,21 @@ static int tegra_qspi_setup(struct spi_device *spi) /* keep default cs state to inactive */ val = tqspi->def_command1_reg; +#if defined(NV_SPI_GET_CHIPSELECT_PRESENT) + val |= QSPI_CS_SEL(spi_get_chipselect(spi, 0)); + + if (spi->mode & SPI_CS_HIGH) + val &= ~QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); + else + val |= QSPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0)); +#else val |= QSPI_CS_SEL(spi->chip_select); + if (spi->mode & SPI_CS_HIGH) val &= ~QSPI_CS_POL_INACTIVE(spi->chip_select); else val |= QSPI_CS_POL_INACTIVE(spi->chip_select); +#endif tqspi->def_command1_reg = val; tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1); diff --git a/scripts/conftest/Makefile b/scripts/conftest/Makefile index e106f2f7..5416a14b 100644 --- a/scripts/conftest/Makefile +++ b/scripts/conftest/Makefile @@ -1,6 +1,6 @@ ########################################################################### # SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. # # Makefile file for NVIDIA Linux conftest ########################################################################### @@ -137,6 +137,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += snd_soc_dai_link_struct_has_c2c_params_arg NV_CONFTEST_FUNCTION_COMPILE_TESTS += snd_soc_of_get_dai_name_has_index_arg NV_CONFTEST_FUNCTION_COMPILE_TESTS += snd_soc_rtd_to_codec NV_CONFTEST_FUNCTION_COMPILE_TESTS += simple_util_dai_init +NV_CONFTEST_FUNCTION_COMPILE_TESTS += spi_get_chipselect NV_CONFTEST_FUNCTION_COMPILE_TESTS += tc_taprio_qopt_offload_struct_has_cmd NV_CONFTEST_FUNCTION_COMPILE_TESTS += tegra_dev_iommu_get_stream_id NV_CONFTEST_FUNCTION_COMPILE_TESTS += tegra_ivc_struct_has_iosys_map diff --git a/scripts/conftest/conftest.sh b/scripts/conftest/conftest.sh index dc48f232..11a454af 100755 --- a/scripts/conftest/conftest.sh +++ b/scripts/conftest/conftest.sh @@ -1,6 +1,6 @@ #!/bin/sh # SPDX-License-Identifier: MIT -# SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved. PATH="${PATH}:/bin:/sbin:/usr/bin" @@ -7238,6 +7238,28 @@ compile_test() { compile_check_conftest "$CODE" "NV_ASOC_SIMPLE_RENAMED_SIMPLE" "" "functions" ;; + spi_get_chipselect) + # + # Determine if the function 'spi_get_chip_select()' is present. + # + # In Linux v6.3, commit 303feb3cc06a ("spi: Add APIs in spi core to set/get + # spi->chip_select and spi->cs_gpiod") added a helper function, + # spi_get_chipselect(), so drivers did not need to access the + # 'spi_device->chip_select' directly. This Linux v6.8, commit 4d8ff6b0991d + # ("spi: Add multi-cs memories support in SPI core") updated the + # 'spi_device->chip_select' to be an array and so using spi_get_chipselect + # to retrieve the chipselect is required for Linux v6.8. + # + CODE=" + #undef CONFIG_ACPI + #include + void conftest_spi_get_chipselect(void) { + spi_get_chipselect(); + }" + + compile_check_conftest "$CODE" "NV_SPI_GET_CHIPSELECT_PRESENT" "" "functions" + ;; + tc_taprio_qopt_offload_struct_has_cmd) # # Determine if struct tc_taprio_qopt_offload has a member named cmd