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PCI: edma_test: Enhance edma stop test
Enable all channels in async mode and stop channel 2 to verify edma stop feature. This stops the dma engine when channels 0, 1 and 2 are in middle of processing descriptors and stops channel 3 before submitting the descriptors. Bug 4620420 Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> Change-Id: Iadff763e299437ef8b7b575c0177968681adb15a Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3133675 (cherry picked from commit 88187c18bf6fe4d64cb9d2964664479492afce5c) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nv-oot/+/3133507 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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@@ -2,7 +2,7 @@
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/*
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* PCIe DMA EPF Library for Tegra PCIe
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*
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* Copyright (C) 2022-2023 NVIDIA Corporation. All rights reserved.
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* Copyright (C) 2022-2024 NVIDIA Corporation. All rights reserved.
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*/
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#ifndef TEGRA_PCIE_EDMA_TEST_COMMON_H
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@@ -195,8 +195,8 @@ static int edmalib_common_test(struct edmalib_common *edma)
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if (EDMA_ABORT_TEST_EN || EDMA_STOP_TEST_EN) {
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edma->edma_ch &= ~0xFF;
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/* only channel 0, 2 is ASYNC, where chan 0 async gets aborted */
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edma->edma_ch |= 0xF5;
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/* All channels in ASYNC, where chan 2 async gets aborted */
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edma->edma_ch |= 0xFF;
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}
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/* FIXME This is causing crash for remote dma when BAR MMIO virt address is used. */
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@@ -457,7 +457,7 @@ static int edmalib_common_test(struct edmalib_common *edma)
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dev_dbg(edma->fdev, "%s: LL EDMA LIB %d, SZ: %u B CH: %d iter %d\n",
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__func__, xfer_type, edma->dma_size, ch, i);
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}
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if (i == 0) {
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if (i == 2) {
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if (EDMA_ABORT_TEST_EN) {
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msleep(edma->stress_count);
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/* TODO support abort test case for T264 */
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