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ASoC: tegra: Add support for 1.2GHz pll base rate

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- For upcoming chips the PLLA base rates are different.
  Added entry to support 1.2GHz base rate.
- Base rate reference:
  Bug 3157662, Comment #77.

Bug 200741253
Bug 3506754

Signed-off-by: Sheetal <sheetal@nvidia.com>
Change-Id: Ib8554b3b6b2f1d0e35e328898f343b1f92870bda
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2704346
(cherry picked from commit 77ec9d06a5dc63d6687be0dfa60136af5e2f98ed)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-5.10/+/2591781
Tested-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Sheetal
2021-09-09 09:53:36 +05:30
committed by Sameer Pujar
parent 9841017f33
commit 125740cada
2 changed files with 10 additions and 3 deletions
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10
sound/soc/tegra/tegra_asoc_utils.c
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@@ -3,7 +3,7 @@
* tegra_asoc_utils.c - Harmony machine ASoC driver
*
* Author: Stephen Warren <swarren@nvidia.com>
* Copyright (c) 2010-2021 NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2010-2022 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
@@ -28,6 +28,7 @@ enum rate_type {
};
unsigned int tegra210_pll_base_rate[NUM_RATE_TYPE] = {338688000, 368640000};
unsigned int tegra186_pll_stereo_base_rate[NUM_RATE_TYPE] = {270950400, 294912000};
unsigned int tegra239_pll_base_rate[NUM_RATE_TYPE] = {1264435200, 1277952000};
unsigned int default_pll_out_stereo_rate[NUM_RATE_TYPE] = {45158400, 49152000};
int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
@@ -350,6 +351,8 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA194;
else if (of_machine_is_compatible("nvidia,tegra234"))
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA234;
else if (of_machine_is_compatible("nvidia,tegra239"))
data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA239;
else {
dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
return -EINVAL;
@@ -382,8 +385,11 @@ int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA186)
data->pll_base_rate = tegra210_pll_base_rate;
else
else if (data->soc < TEGRA_ASOC_UTILS_SOC_TEGRA239)
data->pll_base_rate = tegra186_pll_stereo_base_rate;
else
data->pll_base_rate = tegra239_pll_base_rate;
/*
* If clock parents are not set in DT, configure here to use clk_out_1
* as mclk and extern1 as parent for Tegra30 and higher.